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Patent US5985699A successfully refreshed from Google Patents.
US5985699A
Expired / Lapsed
US
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Method for designing semiconductor integrated circuit
Assignee: NEC Electronics Corp
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Filing: 1998-06-09
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Granted: 1999-11-16
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Expires: 2018-06-09
Abstract
Abstract Cells in which clock skew or variation in transistor properties is to be suppressed are specified and inputted. Next, a method of checking unoccupied cells for arranging dummy cells is specified and inputted. Next, a step of allowing a CAD tool to recognize the unoccupied cells is carried out. In this step, a check is made over a chip so as to see an area in which the cells are not located and to recognize this area as the unoccupied cells. Then, the step of checking whether or not the unoccupied cells are present near the cells to be processed is carried out. In this step, for the cells to be processed, the unoccupied cells are checked by the specified method of checking the unoccupied cells. Then, the dummy cells are arranged in the unoccupied cells.
Inventors
- 👤 Katsuhiko Yokoyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:55
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398; H; H10; H10D; H10D89/00; H10D89/10; G06F2119/00; G06F2119/18; Y; Y02; Y02P; Y02P90/00; Y02P90/02
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
126 words
A method of designing a semiconductor integrated circuit, comprising the steps of: specifying, in optional cells on a chip in a cells base IC, a plurality of cells to be processed in which variation in transistor properties in manufacture or clock skew is to be suppressed; specifying a method of checking unoccupied cells for arranging dummy cells having a dummy gate polysilicon; checking over said chip by a CAD tool so as to see an area in which said cells are not located and recognizing said unoccupied cells; checking whether or not said unoccupied cells are present near said cells to be processed by said specified method of checking unoccupied cells; and arranging said dummy cells in said unoccupied cells near said cells to be processed.
Claim 2
Independent Claim
126 words
A method of designing a semiconductor integrated circuit, comprising the steps of: specifying, in optional cells on a chip in a cells base IC, a plurality of cells to be processed in which variation in transistor properties in manufacture or clock skew is to be suppressed; specifying a method of checking unoccupied cells for arranging dummy cells having a dummy gate polysilicon; checking over said chip by a CAD tool so as to see an area in which said cells are not located and recognizing said unoccupied cells; checking whether or not said unoccupied cells are present near said cells to be processed by said specified method of checking unoccupied cells; and arranging said dummy cells in said unoccupied cells near said cells to be processed.
Claim 3
Independent Claim
121 words
A method of modifying a base design of a semiconductor integrated circuit, said base design having a plurality of cells, some of which contain transistors and others of which are unoccupied, said modifying method comprising the steps of: selecting cells in said plurality of cells in which variations of transistor properties or clock skew of transistors located in those cells are to be suppressed; selecting a method of determining which of said cells in said plurality of cells is unoccupied; determining which of said cells are unoccupied using said selected method; identifying unoccupied cells which are located near said selected cells; and arranging dummy cells having a dummy gate polysilicon in said unoccupied cells which are located near said selected cells.
Claim 4
Independent Claim
121 words
A method of modifying a base design of a semiconductor integrated circuit, said base design having a plurality of cells, some of which contain transistors and others of which are unoccupied, said modifying method comprising the steps of: selecting cells in said plurality of cells in which variations of transistor properties or clock skew of transistors located in those cells are to be suppressed; selecting a method of determining which of said cells in said plurality of cells is unoccupied; determining which of said cells are unoccupied using said selected method; identifying unoccupied cells which are located near said selected cells; and arranging dummy cells having a dummy gate polysilicon in said unoccupied cells which are located near said selected cells.
Claim 5
Dependent Claim
28 words
The method of claim 2, wherein said step of identifying unoccupied cells which are located near said selected cells identifies unoccupied cells which are adjacent said selected cells.
Claim 6
Dependent Claim
15 words
The method of claim 2, wherein said selected cells are selected by a human operator.
Claim 7
Dependent Claim
15 words
The method of claim 2, wherein said selected method is carried out by a machine.
Claim 8
Dependent Claim
14 words
The method of claim 5, wherein said machine is a computer aided design tool.
Claim 9
Dependent Claim
15 words
The method of claim 2, wherein said plurality of cells are arranged in a matrix.
Claim 10
Dependent Claim
15 words
The method of claim 3, wherein said plurality of cells are arranged in a matrix.
Claim 11
Dependent Claim
15 words
The method of claim 4, wherein said plurality of cells are arranged in a matrix.
Claim 12
Dependent Claim
15 words
The method of claim 5, wherein said plurality of cells are arranged in a matrix.
Claim 13
Dependent Claim
15 words
The method of claim 6, wherein said plurality of cells are arranged in a matrix.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |