Method of reducing word line resistance of a semiconductor memory

Claim 2

A process for making a semiconductor memory device having an open bit structure, comprising the steps of: forming adjacent pair of word lines each comprised of a plurality of serially coupled layers of polycrystalline silicon forming gate electrodes of a plurality of transistor memory cells; forming layers of metal extending substantially parallel to said adjacent pairs of word lines; and coupling each said adjacent pair of word lines to a different single word line driver.

Claim 3

The process of claim 1, further comprised of connecting said adjacent pairs of word lines and said layers of metal between each successive pair of adjacent memory cells along said adjacent word lines.

Claim 4

A process of making a semiconductor memory device having an open bit structure, comprising the steps of: forming a plurality of adjacent pairs of word lines with an electrical connection between each said adjacent pair of word lines; and connecting a different, single word line drivers to each said pair of word lines to enable each said different single word line driver to simultaneously drive corresponding said pair of word lines and to enable each said different single word line driver to drive one of the word lines of each said pair of adjacent word lines in response to corresponding selected word line signals, said one of said plurality of word lines exhibiting a reduced resistance.

Claim 5

A process of making a semiconductor memory device having an open bit structure, comprising the steps of: forming a plurality of adjacent pairs of word lines with an electrical connection between each said adjacent pair of word lines; and connecting a different, single word line drivers to each said pair of word lines to enable each said different single word line driver to simultaneously drive corresponding said pair of word lines and to enable each said different single word line driver to drive one of the word lines of each said pair of adjacent word lines in response to corresponding selected word line signals, said one of said plurality of word lines exhibiting a reduced resistance.

Claim 6

The process of claim 3, further comprised of forming said plurality of adjacent pairs of word lines with polycrystalline silicon layers forming serially coupled gate electrodes of memory cells within a memory array formed as a matrix.

Claim 7

The process of claim 4, further comprised of depositing layers of metal forming electrical shunts between different corresponding successive lengths of said polysilicon layers within each of said pair of adjacent word lines.

Claim 8

The process of claim 3, further comprised of forming said plurality of adjacent pairs of word lines by: forming adjacent pairs of word lines each comprised of a plurality of serially coupled layers of polycrystalline silicon forming gate electrodes of a plurality of transistor memory cells; and forming layers of metal extending substantially parallel to said adjacent pairs of word lines.

Claim 9

A process of forming a semiconductor memory device, comprising the steps of: forming a matrix of memory cells with a plurality of word lines, each one of said plurality of word lines capable of accessing a different plurality of said memory cells; and connecting a different, single word line driver to at least two adjacent word lines from said plurality of word lines for enabling said single word line driver to select and drive said two adjacent word lines connected in parallel.

Claim 10

A process of forming a semiconductor memory device, comprising the steps of: forming a matrix of memory cells with a plurality of word lines, each one of said plurality of word lines capable of accessing a different plurality of said memory cells; and connecting a different, single word line driver to at least two adjacent word lines from said plurality of word lines for enabling said single word line driver to select and drive said two adjacent word lines connected in parallel.

Claim 11

The process of claim 7, wherein each of said plurality of word lines is formed by: depositing polysilicon layers forming serially coupled gate electrodes of memory cells within said matrix of memory cells; and depositing metal layers forming electrical shunts between different corresponding successive lengths of said polysilicon layers within each of said at least two of said plurality of word lines.

Claim 12

The process of making a semiconductor memory device having an open bit line structure, comprising the steps: forming a memory array of memory cells; forming a first word line comprising a plurality of first, serially coupled word line resistances to access a first plurality of memory cells in said memory array; forming a second word line comprising a plurality of second, serially coupled word line resistances to access a second plurality of memory cells in said memory array different from said first plurality of memory cells; and connecting a single word line driver to one end of said first word line and said second word line, for enabling said single word line driver to drive one of said first word line and said second word line in response to a word line selection signal and a driver selection signal.

Claim 13

The process of making a semiconductor memory device having an open bit line structure, comprising the steps: forming a memory array of memory cells; forming a first word line comprising a plurality of first, serially coupled word line resistances to access a first plurality of memory cells in said memory array; forming a second word line comprising a plurality of second, serially coupled word line resistances to access a second plurality of memory cells in said memory array different from said first plurality of memory cells; and connecting a single word line driver to one end of said first word line and said second word line, for enabling said single word line driver to drive one of said first word line and said second word line in response to a word line selection signal and a driver selection signal.

Claim 14

The process of claim 9, wherein each of said first and second word lines is formed by: depositing polysilicon layers forming serially coupled gate electrodes of memory cells within said memory array; and depositing metal layers forming electrical shunts between different corresponding successive lengths of said polysilicon layers within each of said first and second word lines.

Claim 15

A process of making a memory device, comprising the steps: forming a memory array of memory cells; forming successive pairs of first and second word lines each pair comprised of a plurality of first layers of a first material forming gate electrodes of the memory cells in said memory array and a second layer of a second material extending substantially parallel to, and being connected to each pair of said first and second word lines; and connecting a single word line driver to said second layer of said second material for communication with each pair of said first and second word lines, for enabling said single word line driver to drive one of said first word line and said second word line during operation of said memory device.

Claim 16

A process of making a memory device, comprising the steps: forming a memory array of memory cells; forming successive pairs of first and second word lines each pair comprised of a plurality of first layers of a first material forming gate electrodes of the memory cells in said memory array and a second layer of a second material extending substantially parallel to, and being connected to each pair of said first and second word lines; and connecting a single word line driver to said second layer of said second material for communication with each pair of said first and second word lines, for enabling said single word line driver to drive one of said first word line and said second word line during operation of said memory device.

Claim 17

The process of claim 11, further comprised of each pair of said first and second word lines being formed by: depositing said plurality of first layers of polycrystalline silicon forming serially coupled gate electrodes of the memory cells within said memory array; and depositing said second layer of metal forming electrical shunts between different corresponding successive lengths of said first layers of polycrystalline silicon of each pair of said first and second word lines.

Claim 18

The process of claim 11, further comprised of said first layers of said first material comprising polycrystalline silicon resistance and said second layer of said second material comprising metal resistance.