US5512504A
Expired / Lapsed
US
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Method of making a memory array with field oxide islands eliminated
Assignee: National Semiconductor Corp
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Filing: 1995-01-09
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Granted: 1996-04-30
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Expires: 2015-01-09
Abstract
Abstract A nonvolatile semiconductor memory, which includes an array of programmable transistor cells, such as EPROM or EEPROM cells, provides electrical isolation without the use of field oxide islands. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supply programming voltages to selected ones of the memory cells. Alternate ones of the select cells are formed as implanted-channel select cells to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state. The implanted-channel select cells are formed by implanting a material into the channel region of each of the implanted-channel select cells to increase the threshold voltage of the cells, thereby preventing the implanted channel select cells from conducting when normal operational voltages are applied.
Inventors
- 👤 Graham Wolstenholme
- 👤 Albert Bergemont
- 👤 Etan Shacham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:53
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/04; G11C16/0491; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
163 words
A method of forming a memory array that includes a plurality of bit lines formed in a substrate, a plurality of rows of memory cells arranged so that, in each row, one memory cell is formed between each pair of adjacent bit lines, and a plurality of rows of select cells arranged so that, in each row, one select cell is formed between each pair of adjacent bit lines, each row of select cells having alternating first and second select cells, the method comprising the steps of: forming a layer of sacrificial oxide on the substrate; forming an implant mask on the layer of sacrificial oxide, the implant mask defining a plurality of channel regions for the second select cells; and implanting the channel regions with a material that increases the threshold voltage of the second select cells so that when a first select cell in a row is biased to conduct a current, the second select cells in the row remain non-conductive.
Claim 2
Independent Claim
163 words
A method of forming a memory array that includes a plurality of bit lines formed in a substrate, a plurality of rows of memory cells arranged so that, in each row, one memory cell is formed between each pair of adjacent bit lines, and a plurality of rows of select cells arranged so that, in each row, one select cell is formed between each pair of adjacent bit lines, each row of select cells having alternating first and second select cells, the method comprising the steps of: forming a layer of sacrificial oxide on the substrate; forming an implant mask on the layer of sacrificial oxide, the implant mask defining a plurality of channel regions for the second select cells; and implanting the channel regions with a material that increases the threshold voltage of the second select cells so that when a first select cell in a row is biased to conduct a current, the second select cells in the row remain non-conductive.
Claim 3
Independent Claim
173 words
A method of forming a memory array that includes a plurality of bit lines formed in a substrate, a plurality of rows of memory cells arranged so that, in each row, one memory cell is formed between each pair of adjacent bit lines, and a plurality of rows of select cells arranged so that, in each row, one select cell is formed between each pair of adjacent bit lines, each row of select cells having alternating first and second select cells, the method comprising the steps of: forming a layer of sacrificial oxide on the substrate; forming an implant mask on the layer of sacrificial oxide, the implant mask defining a portion of a channel region for each second select cell; and implanting the portion of the channel region of each second select cell with a material that increases the threshold voltage of the second select transistor cells so that when a first select cell in a row is biased to conduct a current, the second select cells in the row remain non-conductive.
Claim 4
Independent Claim
173 words
A method of forming a memory array that includes a plurality of bit lines formed in a substrate, a plurality of rows of memory cells arranged so that, in each row, one memory cell is formed between each pair of adjacent bit lines, and a plurality of rows of select cells arranged so that, in each row, one select cell is formed between each pair of adjacent bit lines, each row of select cells having alternating first and second select cells, the method comprising the steps of: forming a layer of sacrificial oxide on the substrate; forming an implant mask on the layer of sacrificial oxide, the implant mask defining a portion of a channel region for each second select cell; and implanting the portion of the channel region of each second select cell with a material that increases the threshold voltage of the second select transistor cells so that when a first select cell in a row is biased to conduct a current, the second select cells in the row remain non-conductive.
Claim 5
Dependent Claim
14 words
The method of claim 1 wherein the substrate includes a P - -type substrate.
Claim 6
Dependent Claim
14 words
The method of claim 2 wherein the substrate includes a P - -type substrate.
Claim 7
Dependent Claim
25 words
The method of claim 1 wherein, in going down each column of the array, every other select cell is formed as a second select cell.
Claim 8
Dependent Claim
25 words
The method of claim 2 wherein, in going down each column of the array, every other select cell is formed as a second select cell.
Claim 9
Dependent Claim
10 words
The method of claim 1 wherein the material includes boron.
Claim 10
Dependent Claim
10 words
The method of claim 2 wherein the material includes boron.
Claim 11
Dependent Claim
12 words
The method of claim 1 wherein the material includes BF 2 .
Claim 12
Dependent Claim
12 words
The method of claim 1 wherein the material includes BF 2 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-30 | 1999-10-30 | 2000-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-30 | 2003-10-30 | 2004-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-30 | 2007-10-30 | 2008-04-30 | $7700.00 | Window Closed / Lapsed |