Master slice type semiconductor integrated circuit having sea of gates

Claim 2

A master slice type semiconductor integrated circuit comprising: a semiconductor chip; input/output cells arranged in a peripheral portion of said semiconductor chip; and basic cells arranged in a portion of said semiconductor chip excluding the peripheral portion of said semiconductor chip, each of said basic cells including a first portion containing complementary MOSFETs in the form of pairs of one N-channel MOSFET and one P-channel MOSFET, the P-channel MOSFETs of said pairs comprising first and second P-type regions spaced from each other in a first column direction by an N-type channel region insulatingly overlaid by a conductive gate electrode; the N-channel MOSFETs of said pairs comprising first and second N-type regions spaced from each other in said first column direction by an P-type channel region insulatingly overlaid by a conductive gate electrode; said first regions, second regions, channel regions, and gate electrodes of the N-channel MOSFETs of said pairs being located adjacent said first regions, second regions, channel regions, and gate electrodes of the P-channel MOSFETs of said pairs, respectively, in a direction perpendicular to said first column direction; each of said basic cells further including a second portion containing MOSFETs of a single channel type; said second portion of each of said basic cells being located adjacent said first portion of a respective one of said basic cells in a direction perpendicular to said first column direction; said second portion of each of said basic cells containing at least one MOSFET comprising first and second regions of a first conductivity type, spaced from each other in said first column direction by a second conductivity type channel region insulatingly overlaid by a conductive gate electrode; the conductive gate electrode of said at least one MOSFET being offset in said first column direction from the conductive gates of any of the MOSFETs of said first portion containing complementary MOSFETs.

Claim 3

A master slice type semiconductor integrated circuit as claimed in claim 1, wherein the conductive gate electrode of said P-channel MOSFET and the conductive gate electrode of said N-channel MOSFET in each of said pairs are integrally formed by a common electrode.

Claim 4

A master slice type semiconductor integrated circuit as claimed in claim 1, wherein said basic cells form a plurality of basic cell columns which are arranged in a direction perpendicular to said first column direction so that said first portion of said adjacent basic cell columns are adjacent each other and said second portion of said adjacent basic cell columns are adjacent each other.

Claim 5

A master slice type semiconductor integrated circuit as claimed in claim 3, wherein between two of said basic cell columns having adjacent first portions, the conductive gate electrode of said second portion in one of said two basic cell columns and the conductive gate electrode of said second portion in the other one of said two basic cell columns are offset in mutually opposite directions along said first column direction.

Claim 6

A master slice type semiconductor integrated circuit as claimed in claim 3, wherein between two of said basic cell columns having adjacent second portions, the conductive gate electrode of said second portion in one of said two basic cell columns and the conductive gate electrode of said second portion in the other one of said two basic cell columns are offset in mutually opposite directions along said first column direction.

Claim 7

A master slice type semiconductor integrated circuit as claimed in claim 1, wherein said P-channel MOSFETs include first and second P-channel MOSFETs and said N-channel MOSFETs include first and second N-channel MOSFETs.

Claim 8

A master slice type semiconductor integrated circuit as claimed in claim 6, wherein said second region of said first P-channel MOSFET and said first region of said second P-channel MOSFET are formed by a common P-type region, and said second region of said second N-channel MOSFET and said first region of said first N-channel MOSFET are formed by a common N-type region.

Claim 9

A master slice type semiconductor integrated circuit as claimed in claim 7, wherein said N-channel MOSFETs further include third, fourth, fifth and sixth N-channel MOSFETs in said second portion, said third and fourth N-channel MOSFETs are arranged in said first column direction and include isolated first, second and third N-type regions, said fifth and sixth N-channel MOSFETs are arranged in said first column direction and include isolated fourth, fifth and sixth N-type regions, said first through sixth N-type regions are arranged in a direction perpendicular to said first column direction, and said fourth and sixth N-channel MOSFETs have conductive gate electrodes which are offset in said first column direction.

Claim 10

A master slice type semiconductor integrated circuit as claimed in claim 8, wherein said conductor gate electrodes of said fourth and sixth N-channel MOSFETs are formed by a linear integral electrode, and said third and fifth N-channel MOSFETs have conductor gate electrodes which are formed by a curved integral electrode.

Claim 11

A master slice type semiconductor integrated circuit as claimed in claim 9, wherein said basic cells form a plurality of basic cell columns which are arranged in a direction perpendicular to said first column direction, said conductive gate electrodes of said fourth and sixth N-channel MOSFETs in said second portion of one of said basic cell columns and said conductive gate electrodes of said fourth and sixth N-channel MOSFETs in said second portion of another one of said basic cell columns are respectively formed by an integral common electrode, and said conductive gate electrodes of said third and fifth N-channel MOSFETs of one of said basic cell columns and said conductive gate electrodes of said third and fifth N-channel MOSFETs of another one of said basic cell columns are respectively formed by an integral common electrode.

Claim 12

A master slice type semiconductor integrated circuit as claimed in claim 7, wherein said second portion is located adjacent said first portion at both ends of said first portion along a direction perpendicular to said first column direction.

Claim 13

A master slice type semiconductor integrated circuit as claimed in claim 8, wherein a length of said first region of said MOSFETs in said second portion along said first column direction is greater than the length of said second region of said MOSFETs in said second portion.

Claim 14

A master slice type semiconductor integrated circuit as claimed in claim 8, wherein a width of said conductive gate electrode on both sides of said channel region along the direction perpendicular to said first column direction is greater than that at a part overlying said channel region for each of said P-channel MOSFETs and said N-channel MOSFETs.

Claim 15

A master slice type semiconductor integrated circuit as claimed in claim 8, wherein a width of said conductive gate electrode of said P-channel and N-channel MOSFETs within said first portion along the direction perpendicular to said first column direction is greater than a width of said conductive gate electrodes of said MOSFETs within said second portion.

Claim 16

A master slice type semiconductor integrated circuit operable as a single port random access memory comprising: a semiconductor chip; input/output cells arranged in a peripheral portion of said semiconductor chip; a plurality of word lines; a plurality of bit lines; a first power source line for receiving a first power source voltage; a second power source line for receiving a second power source voltage; and basic cells arranged in a portion of said semiconductor chip excluding the peripheral portion of said semiconductor chip; each of said basic cells including a first portion containing complementary MOSFETs in the form of two pairs of one N-channel MOSFET and one P-channel MOSFET, the P-channel MOSFETs of said two pairs comprising first and second P-type regions spaced from each other in a first column direction by an N-type channel region insulatingly overlaid by a conductive gate electrode, the N-channel MOSFETs of said two pairs comprising first and second N-type regions spaced from each other in said first column direction by a P-type channel region insulatingly overlaid by a conductive gate electrode, said first regions, second regions, channel regions and gate electrodes of the N-channel MOSFETs of said pairs being located adjacent said first regions, second regions, channel regions and gate electrodes of the P-channel MOSFETs of said pairs, respectively, in a direction perpendicular to said first column direction, each of said basic cells further including a second portion containing four MOSFETs of a single channel type, said second portion of each of said basic cells being located adjacent said first portion of a respective one of said basic cells in a direction perpendicular to said first column direction, said second portion of each of said basic cells containing at least one MOSFET comprising first and second regions of a first conductivity type, spaced from each other in said first column direction by a second conductivity type channel region insulatingly overlaid by a conductive gate electrode, the conductive gate electrode of said at least one MOSFET being offset in said first column direction from the conductive gates of any of the MOSFETs of said first portion containing complementary MOSFETs, each of said basic cells forming a memory cell including a flip-flop formed by the MOSFETs within said first portion, each of the MOSFETs within said second portion forming a transfer gate which is connected to a corresponding one of the bit lines at the conductive gate electrode of the MOSFET within said second portion, each of said transfer gates coupled to the flip-flop of one memory cell being connected to a common word line, the N-type region of the P-channel MOSFET being connected to said first power source line, the P-type channel region of the N-channel MOSFET being connected to said second power source line.

Claim 17

A master slice type semiconductor integrated circuit operable as a single port random access memory comprising: a semiconductor chip; input/output cells arranged in a peripheral portion of said semiconductor chip; a plurality of word lines; a plurality of bit lines; a first power source line for receiving a first power source voltage; a second power source line for receiving a second power source voltage; and basic cells arranged in a portion of said semiconductor chip excluding the peripheral portion of said semiconductor chip; each of said basic cells including a first portion containing complementary MOSFETs in the form of two pairs of one N-channel MOSFET and one P-channel MOSFET, the P-channel MOSFETs of said two pairs comprising first and second P-type regions spaced from each other in a first column direction by an N-type channel region insulatingly overlaid by a conductive gate electrode, the N-channel MOSFETs of said two pairs comprising first and second N-type regions spaced from each other in said first column direction by a P-type channel region insulatingly overlaid by a conductive gate electrode, said first regions, second regions, channel regions and gate electrodes of the N-channel MOSFETs of said pairs being located adjacent said first regions, second regions, channel regions and gate electrodes of the P-channel MOSFETs of said pairs, respectively, in a direction perpendicular to said first column direction, each of said basic cells further including a second portion containing four MOSFETs of a single channel type, said second portion of each of said basic cells being located adjacent said first portion of a respective one of said basic cells in a direction perpendicular to said first column direction, said second portion of each of said basic cells containing at least one MOSFET comprising first and second regions of a first conductivity type, spaced from each other in said first column direction by a second conductivity type channel region insulatingly overlaid by a conductive gate electrode, the conductive gate electrode of said at least one MOSFET being offset in said first column direction from the conductive gates of any of the MOSFETs of said first portion containing complementary MOSFETs, each of said basic cells forming a memory cell including a flip-flop formed by the MOSFETs within said first portion, each of the MOSFETs within said second portion forming a transfer gate which is connected to a corresponding one of the bit lines at the conductive gate electrode of the MOSFET within said second portion, each of said transfer gates coupled to the flip-flop of one memory cell being connected to a common word line, the N-type region of the P-channel MOSFET being connected to said first power source line, the P-type channel region of the N-channel MOSFET being connected to said second power source line.

Claim 18

A master slice type semiconductor integrated circuit operable as a dual port random access memory comprising: a semiconductor chip; input/output cells arranged in a peripheral portion of said semiconductor chip; a plurality of word lines; a plurality of bit lines; a first power source line for receiving a first power source voltage; a second power source line for receiving a second power source voltage; and basic cells arranged in a portion of said semiconductor chip excluding the peripheral portion of said semiconductor chip; each of said basic cells including a first portion containing complementary MOSFETs in the form of two pairs of one N-channel MOSFET and one P-channel MOSFET, the P-channel MOSFETs of said two pairs comprising first and second P-type regions spaced from each other in a first column direction by an N-type channel region insulatingly overlaid by a conductive gate electrode, the N-channel MOSFETs of said two pairs comprising first and second N-type regions spaced from each other in said first column direction by a P-type channel region insulatingly overlaid by a conductive gate electrode, said first regions, second regions, channel regions and gate electrodes of the N-channel MOSFETs of said pairs being located adjacent said first regions, second regions, channel regions and gate electrodes of the P-channel MOSFETs of said pairs, respectively, in a direction perpendicular to said first column direction, each of said basic cells further including a second portion containing four MOSFETs of a single channel type, said second portion of each of said basic cells being located adjacent said first portion of a respective one of said basic cells in a direction perpendicular to said first column direction, said second portion of each of said basic cells containing at least one MOSFET comprising first and second regions of a first conductivity type, spaced from each other in said first column direction by a second conductivity type channel region insulatingly overlaid by a conductive gate electrode, the conductive gate electrode of said at least one MOSFET being offset in said first column direction from the conductive gates of any of the MOSFETs of said first portion containing complementary MOSFETs, each of said basic cells forming a memory cell including a flip-flop formed by the MOSFETs within said first portion, each of the MOSFETs within said second portion forming a transfer gate which is coupled to a corresponding one of the bit lines and to a corresponding one of the word lines at the conductive gate electrode of the MOSFET within said second portion, the N-type channel region of the P-channel MOSFET being connected to said first power source line, the P-type channel region of the N-channel MOSFET being connected to said second power source line.

Claim 19

A master slice type semiconductor integrated circuit operable as a dual port random access memory comprising: a semiconductor chip; input/output cells arranged in a peripheral portion of said semiconductor chip; a plurality of word lines; a plurality of bit lines; a first power source line for receiving a first power source voltage; a second power source line for receiving a second power source voltage; and basic cells arranged in a portion of said semiconductor chip excluding the peripheral portion of said semiconductor chip; each of said basic cells including a first portion containing complementary MOSFETs in the form of two pairs of one N-channel MOSFET and one P-channel MOSFET, the P-channel MOSFETs of said two pairs comprising first and second P-type regions spaced from each other in a first column direction by an N-type channel region insulatingly overlaid by a conductive gate electrode, the N-channel MOSFETs of said two pairs comprising first and second N-type regions spaced from each other in said first column direction by a P-type channel region insulatingly overlaid by a conductive gate electrode, said first regions, second regions, channel regions and gate electrodes of the N-channel MOSFETs of said pairs being located adjacent said first regions, second regions, channel regions and gate electrodes of the P-channel MOSFETs of said pairs, respectively, in a direction perpendicular to said first column direction, each of said basic cells further including a second portion containing four MOSFETs of a single channel type, said second portion of each of said basic cells being located adjacent said first portion of a respective one of said basic cells in a direction perpendicular to said first column direction, said second portion of each of said basic cells containing at least one MOSFET comprising first and second regions of a first conductivity type, spaced from each other in said first column direction by a second conductivity type channel region insulatingly overlaid by a conductive gate electrode, the conductive gate electrode of said at least one MOSFET being offset in said first column direction from the conductive gates of any of the MOSFETs of said first portion containing complementary MOSFETs, each of said basic cells forming a memory cell including a flip-flop formed by the MOSFETs within said first portion, each of the MOSFETs within said second portion forming a transfer gate which is coupled to a corresponding one of the bit lines and to a corresponding one of the word lines at the conductive gate electrode of the MOSFET within said second portion, the N-type channel region of the P-channel MOSFET being connected to said first power source line, the P-type channel region of the N-channel MOSFET being connected to said second power source line.

Claim 20

A master slice type semiconductor integrated circuit operable as a read only memory comprising: a semiconductor chip; input/output cells arranged in a peripheral portion of said semiconductor chip; a plurality of word lines; a plurality of bit lines; a first power source line for receiving a first power source voltage; a second power source line for receiving a second power source voltage; and basic cells arranged in a portion of said semiconductor chip excluding the peripheral portion of said semiconductor chip; each of said basic cells including a first portion containing complementary MOSFETs in the form of two pairs of one N-channel MOSFET and one P-channel MOSFET, the P-channel MOSFETs of said two pairs comprising first and second P-type regions spaced from each other in a first column direction by an N-type channel region insulatingly overlaid by a conductive gate electrode, the N-channel MOSFETs of said two pairs comprising first and second N-type regions spaced from each other in said first column direction by a P-type channel region insulatingly overlaid by a conductive gate electrode, said first regions, second regions, channel regions and gate electrodes of the N-channel MOSFETs of said pairs being located adjacent said first regions, second regions, channel regions and gate electrodes of the P-channel MOSFETs of said pairs, respectively, in a direction perpendicular to said first column direction, each of said basic cells further including a second portion containing four MOSFETs of a single channel type, said second portion of each of said basic cells being located adjacent said first portion of a respective one of said basic cells in a direction perpendicular to said first column direction, said second portion of each of said basic cells containing at least one MOSFET comprising first and second regions of a first conductivity type, spaced from each other in said first column direction by a second conductivity type channel region insulatingly overlaid by a conductive gate electrode, the conductive gate electrode of said at least one MOSFET being offset in said first column direction from the conductive gates of any of the MOSFETs of said first portion containing complementary MOSFETs, each of said basic cells forming memory cells by the MOSFETs within said second portion, each of said memory cells being connected to one of the word lines and to one of the bit lines, said first power source line being connected in common to the N-channel region of the P-channel MOSFET within said first portion and the first conductivity type first and second regions of the MOSFET being connected within said second portion, said second power source line being connected in common to the first and second P-type regions of the P-channel MOSFET within said first portion and the P-type channel region of the N-channel MOSFET within said first portion.

Claim 21

A master slice type semiconductor integrated circuit operable as a read only memory comprising: a semiconductor chip; input/output cells arranged in a peripheral portion of said semiconductor chip; a plurality of word lines; a plurality of bit lines; a first power source line for receiving a first power source voltage; a second power source line for receiving a second power source voltage; and basic cells arranged in a portion of said semiconductor chip excluding the peripheral portion of said semiconductor chip; each of said basic cells including a first portion containing complementary MOSFETs in the form of two pairs of one N-channel MOSFET and one P-channel MOSFET, the P-channel MOSFETs of said two pairs comprising first and second P-type regions spaced from each other in a first column direction by an N-type channel region insulatingly overlaid by a conductive gate electrode, the N-channel MOSFETs of said two pairs comprising first and second N-type regions spaced from each other in said first column direction by a P-type channel region insulatingly overlaid by a conductive gate electrode, said first regions, second regions, channel regions and gate electrodes of the N-channel MOSFETs of said pairs being located adjacent said first regions, second regions, channel regions and gate electrodes of the P-channel MOSFETs of said pairs, respectively, in a direction perpendicular to said first column direction, each of said basic cells further including a second portion containing four MOSFETs of a single channel type, said second portion of each of said basic cells being located adjacent said first portion of a respective one of said basic cells in a direction perpendicular to said first column direction, said second portion of each of said basic cells containing at least one MOSFET comprising first and second regions of a first conductivity type, spaced from each other in said first column direction by a second conductivity type channel region insulatingly overlaid by a conductive gate electrode, the conductive gate electrode of said at least one MOSFET being offset in said first column direction from the conductive gates of any of the MOSFETs of said first portion containing complementary MOSFETs, each of said basic cells forming memory cells by the MOSFETs within said second portion, each of said memory cells being connected to one of the word lines and to one of the bit lines, said first power source line being connected in common to the N-channel region of the P-channel MOSFET within said first portion and the first conductivity type first and second regions of the MOSFET being connected within said second portion, said second power source line being connected in common to the first and second P-type regions of the P-channel MOSFET within said first portion and the P-type channel region of the N-channel MOSFET within said first portion.

Claim 22

A master slice type semiconductor integrated circuit operable as a programmable logic array comprising: a semiconductor chip; input/output cells arranged in a peripheral portion of said semiconductor chip; basic cells arranged in a portion of said semiconductor chip excluding the peripheral portion of said semiconductor chip; input lines; first product term lines; second product term lines connected to said first product term lines; an AND plane; and an OR plane, each of said basic cells including a first portion containing complementary MOSFETs in the form of two pairs of one N-channel MOSFET and one P-channel MOSFET, the P-channel MOSFETs of said two pairs comprising first and second P-type regions spaced from each other in a first column direction by an N-type channel region insulatingly overlaid by a conductive gate electrode, the N-channel MOSFETs of said two pairs comprising first and second N-type regions spaced from each other in said first column direction by a P-type channel region insulatingly overlaid by a conductive gate electrode, said first regions, second regions, channel regions and gate electrodes of the N-channel MOSFETs of said pairs being located adjacent said first regions, second regions, channel regions and gate electrodes of the P-channel MOSFETs of said pairs, respectively, in a direction perpendicular to said first column direction, each of said basic cells further including a second portion containing four MOSFETs of a single channel type, said second portion of each of said basic cells being located adjacent said first portion of a respective one of said basic cells in a direction perpendicular to said first column direction, said second portion of each of said basic cells containing at least one MOSFET comprising first and second regions of a first conductivity type, spaced from each other in said first column direction by a second conductivity type channel region insulatingly overlaid by a conductive gate electrode, the conductive gate electrode of said at least one MOSFET being offset in said first column direction from the conductive gates of any of the MOSFETs of said first portion containing complementary MOSFETs, said AND plane including said first portion having the N-channel MOSFETs located at intersections of said input lines and said first product terminal lines, said OR plane including said second portion having the MOSFETs located at intersections of said second product term lines and said output lines.

Claim 23

A master slice type semiconductor integrated circuit operable as a programmable logic array comprising: a semiconductor chip; input/output cells arranged in a peripheral portion of said semiconductor chip; basic cells arranged in a portion of said semiconductor chip excluding the peripheral portion of said semiconductor chip; input lines; first product term lines; second product term lines connected to said first product term lines; an AND plane; and an OR plane, each of said basic cells including a first portion containing complementary MOSFETs in the form of two pairs of one N-channel MOSFET and one P-channel MOSFET, the P-channel MOSFETs of said two pairs comprising first and second P-type regions spaced from each other in a first column direction by an N-type channel region insulatingly overlaid by a conductive gate electrode, the N-channel MOSFETs of said two pairs comprising first and second N-type regions spaced from each other in said first column direction by a P-type channel region insulatingly overlaid by a conductive gate electrode, said first regions, second regions, channel regions and gate electrodes of the N-channel MOSFETs of said pairs being located adjacent said first regions, second regions, channel regions and gate electrodes of the P-channel MOSFETs of said pairs, respectively, in a direction perpendicular to said first column direction, each of said basic cells further including a second portion containing four MOSFETs of a single channel type, said second portion of each of said basic cells being located adjacent said first portion of a respective one of said basic cells in a direction perpendicular to said first column direction, said second portion of each of said basic cells containing at least one MOSFET comprising first and second regions of a first conductivity type, spaced from each other in said first column direction by a second conductivity type channel region insulatingly overlaid by a conductive gate electrode, the conductive gate electrode of said at least one MOSFET being offset in said first column direction from the conductive gates of any of the MOSFETs of said first portion containing complementary MOSFETs, said AND plane including said first portion having the N-channel MOSFETs located at intersections of said input lines and said first product terminal lines, said OR plane including said second portion having the MOSFETs located at intersections of said second product term lines and said output lines.