US5172335A
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Semiconductor memory with divided bit load and data bus lines
Assignee: Hitachi Ltd
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Filing: 1991-07-01
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Granted: 1992-12-15
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Expires: 2011-07-01
Abstract
Abstract A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).
Inventors
- 👤 Toshio Sasaki
- 👤 Osamu Minato
- 👤 Shigeru Honjiyo
- 👤 Koichiro Ishibashi
- 👤 Toshiaki Masuhara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
253 words
In a divided mat semiconductor memory which includes: a plurality of memory mats, each mat divided into a first mat part and a second mat part, and each mat part including a plurality of memory cells; a plurality of bit lines, each of which addresses a column of memory cells of one of the first and second mat parts; a plurality of word lines divided into first word line fractions which each address only memory cells in rows of the first mat part and second word line fractions which each address only memory cells of rows of the second mat part; a y-decoder means for selecting along the bit lines; an x-decoder means for selecting among the first word line fractions and the second word line fractions, the first mat part being in closer physical proximity to the x-decoder means than the second mat part; THE IMPROVEMENTS COMPRISING: (1) the x-decoder means (14) being connected directly with the first word line fractions (16a) without intervening logic devices connected electrically between the x-decoder means and the first word line fractions for addressing only memory cells included in the first mat part (30a); and, (2) a wiring means (50) for directly connecting the x-decoder means (14) across the first mat part (30a) to the second word line fractions electrically between the x-decoder means and the second word line fractions for addressing only memory cells included in the second mat part (30b), the wiring means (50) being electrically isolated from the first word line fractions (16a).
Claim 2
Dependent Claim
253 words
In a divided mat semiconductor memory which includes: a plurality of memory mats, each mat divided into a first mat part and a second mat part, and each mat part including a plurality of memory cells; a plurality of bit lines, each of which addresses a column of memory cells of one of the first and second mat parts; a plurality of word lines divided into first word line fractions which each address only memory cells in rows of the first mat part and second word line fractions which each address only memory cells of rows of the second mat part; a y-decoder means for selecting along the bit lines; an x-decoder means for selecting among the first word line fractions and the second word line fractions, the first mat part being in closer physical proximity to the x-decoder means than the second mat part; THE IMPROVEMENTS COMPRISING: (1) the x-decoder means (14) being connected directly with the first word line fractions (16a) without intervening logic devices connected electrically between the x-decoder means and the first word line fractions for addressing only memory cells included in the first mat part (30a); and, (2) a wiring means (50) for directly connecting the x-decoder means (14) across the first mat part (30a) to the second word line fractions electrically between the x-decoder means and the second word line fractions for addressing only memory cells included in the second mat part (30b), the wiring means (50) being electrically isolated from the first word line fractions (16a).
Claim 3
Dependent Claim
296 words
A semiconductor memory comprising: a plurality of memory mats, each mat is divided into a first mat part (30a) and a second part (30b), and each mat part including a plurality of memory cells; a plurality of bit lines which address columns of the memory cells; a plurality of first word line fractions (16a) which address only memory cells of rows of the first mat part; a plurality of second word line fractions (16b) which address only memory cells of rows of the second mat part, the second word line fractions having electrically isolated from the first word line fractions; a y-decoder means for selecting among the bit lines; an x-decoder means (14) for selecting among the first and second word line fractions, the first mat part being in closer physical proximity to the x-decoder means than the second mat part, the x-decoder means being connected directly with the first word line fractions without intervening logic devices for addressing memory cells included in the first mat part; wiring segments (50), which are different electrical structures than the first word line fractions (16a), connecting the x-decoder means (14) across the first mat part (30a) without any logic devices electrically connected between the x-decoder means and the wiring segments; and a plurality of electrical contact points (52), each electrical contact point extending directly between one of the wiring segments (50) and one the second word line fractions (16b) to provide direct electric communication therebetween without any logic devices electrically connected between the wiring segments and the second word line fractions, such that the x-decoder means directly addressed memroy cells in the second mat part (30b) through the wiring segments (50) without any logic devices electrically connected between the x-decoder means (14) and the second word line fractions (16b).
Claim 4
Dependent Claim
296 words
A semiconductor memory comprising: a plurality of memory mats, each mat is divided into a first mat part (30a) and a second part (30b), and each mat part including a plurality of memory cells; a plurality of bit lines which address columns of the memory cells; a plurality of first word line fractions (16a) which address only memory cells of rows of the first mat part; a plurality of second word line fractions (16b) which address only memory cells of rows of the second mat part, the second word line fractions having electrically isolated from the first word line fractions; a y-decoder means for selecting among the bit lines; an x-decoder means (14) for selecting among the first and second word line fractions, the first mat part being in closer physical proximity to the x-decoder means than the second mat part, the x-decoder means being connected directly with the first word line fractions without intervening logic devices for addressing memory cells included in the first mat part; wiring segments (50), which are different electrical structures than the first word line fractions (16a), connecting the x-decoder means (14) across the first mat part (30a) without any logic devices electrically connected between the x-decoder means and the wiring segments; and a plurality of electrical contact points (52), each electrical contact point extending directly between one of the wiring segments (50) and one the second word line fractions (16b) to provide direct electric communication therebetween without any logic devices electrically connected between the wiring segments and the second word line fractions, such that the x-decoder means directly addressed memroy cells in the second mat part (30b) through the wiring segments (50) without any logic devices electrically connected between the x-decoder means (14) and the second word line fractions (16b).
Claim 5
Dependent Claim
277 words
A divider mat semiconductor memory comprising: a plurality of memory mats, each mat being divide dinto a first mat part (30a) and a second mat part (30b), and each mat part including a plurality of memory cells; a plurality of bit lines, each bit line addressing a column of memory cells of one of the first and second mat parts; a plurality of first word line fractions (16a), each first word line fraction addressing a row of memory cells of the first mat part only; a plurality of second word line fractions (16b), each second word line fraction addressing rows of memory cells of the second mat part only; a y-decoder means for selecting among the plurality of bit lines; an x-decoder means for selecting among the first and second word line fractions, the first mat part being in closer physical proximity to the x-decoder means than the second mat part, the x-decoder means being connected directly with the first word line fractions without intervening logic devices for addressing only memory cells included in the first mat part; first wiring segments (50) connected directly with the x-decoder means, extending over the first mat part (30a), and connected by the first contact points (52) directly with first ends of the second word line fractions (16b) without logic devices electrically connected between the x-decoder means and the second word line fractions; and second working segments (56) extending over the second mat part (30b) and connected by second contact points (54) directly with second ends of the second word line fractions (16b) without logic devices electrically connected between the second wiring segments (56) and the second word line fractions (16b).
Claim 6
Dependent Claim
277 words
A divider mat semiconductor memory comprising: a plurality of memory mats, each mat being divide dinto a first mat part (30a) and a second mat part (30b), and each mat part including a plurality of memory cells; a plurality of bit lines, each bit line addressing a column of memory cells of one of the first and second mat parts; a plurality of first word line fractions (16a), each first word line fraction addressing a row of memory cells of the first mat part only; a plurality of second word line fractions (16b), each second word line fraction addressing rows of memory cells of the second mat part only; a y-decoder means for selecting among the plurality of bit lines; an x-decoder means for selecting among the first and second word line fractions, the first mat part being in closer physical proximity to the x-decoder means than the second mat part, the x-decoder means being connected directly with the first word line fractions without intervening logic devices for addressing only memory cells included in the first mat part; first wiring segments (50) connected directly with the x-decoder means, extending over the first mat part (30a), and connected by the first contact points (52) directly with first ends of the second word line fractions (16b) without logic devices electrically connected between the x-decoder means and the second word line fractions; and second working segments (56) extending over the second mat part (30b) and connected by second contact points (54) directly with second ends of the second word line fractions (16b) without logic devices electrically connected between the second wiring segments (56) and the second word line fractions (16b).
Claim 7
Dependent Claim
92 words
In the divided mat semiconductor memory of claim 1, THE FURTHER IMPROVEMENTS COMPRISING the wiring means including: a plurality of first wiring segments, each first wiring segment extending across the first mat part and directly connecting the x-decoder means with the second word line fractions without active electrical devices connected with the first wiring segments between the x-decoder means and the second word line fractions; and a plurality of second wiring segments, each second wiring segment being connected with one of the first wiring segments and extending across the second mat part.
Claim 8
Dependent Claim
264 words
A divided mat semiconductor memory comprising: a plurality of memory mate, each mat divided into a first mat part and a second mat part, and each mat part including a plurality of memory cells, the first mat part being in closer physical proximity to the x-decoder means than the second mat part; a plurality of bit lines, each bit line concurrently addresses a memory cell column of one of the first and second mat parts; a plurality of word lines divided into (i) electrically isolated first word line fractions, each of which addresses a memory cell row of the first mat part only, and (ii) second word line fractions, each of which addresses a memory cell row of the second mat part only; a y-decoder means for selecting among the bit lines; an x-decoder means for selecting among the first and the second word line fractions, the x-decoder means being connected directly and ungated with the first word line fractions for addressing each row of memory cells of the first mat part only, the x-decoder means being connected directly with the first line fractions without intervening gating devices connected electrically between the x-decoder means and the first word line fractions; and, a wiring means for directly and ungatedly connecting the x-decoder means across the first mat part to the second word line fractions without intervening gating devices connected electrically between the x-decoder means and the second word line fractions for addressing each row of memory cells of the second mat part only, the wiring means being electrically isolated from the first word line fractions.
Claim 9
Dependent Claim
264 words
A divided mat semiconductor memory comprising: a plurality of memory mate, each mat divided into a first mat part and a second mat part, and each mat part including a plurality of memory cells, the first mat part being in closer physical proximity to the x-decoder means than the second mat part; a plurality of bit lines, each bit line concurrently addresses a memory cell column of one of the first and second mat parts; a plurality of word lines divided into (i) electrically isolated first word line fractions, each of which addresses a memory cell row of the first mat part only, and (ii) second word line fractions, each of which addresses a memory cell row of the second mat part only; a y-decoder means for selecting among the bit lines; an x-decoder means for selecting among the first and the second word line fractions, the x-decoder means being connected directly and ungated with the first word line fractions for addressing each row of memory cells of the first mat part only, the x-decoder means being connected directly with the first line fractions without intervening gating devices connected electrically between the x-decoder means and the first word line fractions; and, a wiring means for directly and ungatedly connecting the x-decoder means across the first mat part to the second word line fractions without intervening gating devices connected electrically between the x-decoder means and the second word line fractions for addressing each row of memory cells of the second mat part only, the wiring means being electrically isolated from the first word line fractions.
Claim 10
Dependent Claim
261 words
A divided mat semiconductor memory comprising: a plurality of memory mats, each mat divided into a first mat part and a second mat part, and each mat part including a plurality of memory cells, the first mat part being in closer physical proximity to the x-decoder means than the second mat part; a plurality of bit lines, each bit line concurrently addresses a memory cell column of one of the first and second mat parts; a plurality of word lines divided into electrically isolated first word line fractions and second word line fractions, each first word line fraction addresses a memory cell row of the first mat part only and each second word line fraction addresses a memory cell row of the scond mat part only; a y-decoder means for selecting among the bit lines; an x-decoder means for selecting among the first and the second word line fractions, the x-decoder means being connected directly with the first word line fractions for addressing each memory cell row of the first mat part only, the x-decoder means being connected directly with the first line fractions without intervening driver devices connected electrically between the x-decoder means and the first word line fractions; and a wiring means for directly connecting the x-decoder means across the first mat part to the second word line fractions without intervening driver devices connected electrically between the x-decoder means and the second word line fractions for addressing each memory cell row of the second mat part only, the wiring means being electrically discrete from the first word line fractions.
Claim 11
Dependent Claim
261 words
A divided mat semiconductor memory comprising: a plurality of memory mats, each mat divided into a first mat part and a second mat part, and each mat part including a plurality of memory cells, the first mat part being in closer physical proximity to the x-decoder means than the second mat part; a plurality of bit lines, each bit line concurrently addresses a memory cell column of one of the first and second mat parts; a plurality of word lines divided into electrically isolated first word line fractions and second word line fractions, each first word line fraction addresses a memory cell row of the first mat part only and each second word line fraction addresses a memory cell row of the scond mat part only; a y-decoder means for selecting among the bit lines; an x-decoder means for selecting among the first and the second word line fractions, the x-decoder means being connected directly with the first word line fractions for addressing each memory cell row of the first mat part only, the x-decoder means being connected directly with the first line fractions without intervening driver devices connected electrically between the x-decoder means and the first word line fractions; and a wiring means for directly connecting the x-decoder means across the first mat part to the second word line fractions without intervening driver devices connected electrically between the x-decoder means and the second word line fractions for addressing each memory cell row of the second mat part only, the wiring means being electrically discrete from the first word line fractions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-15 | 1996-06-15 | 1996-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-15 | 2000-06-15 | 2000-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-15 | 2004-06-15 | 2004-12-15 | $7700.00 | Window Closed / Lapsed |