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US4802132A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Toshiba Corp
•
Filing: 1987-11-18
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Granted: 1989-01-31
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Expires: 2007-11-18
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Abstract

Abstract A semiconductor memory device includes a memory cell array having N memory blocks; N buffers respectively connected to the memory blocks; drivers, data selection circuits for selecting data to or from the drivers, a plurality of data buses connected to the data selection circuits, and a control unit for supplying control signals to said data selection circuits in each operation cycle, causing the data buses to be sequentially connected to the drivers via the data selection circuits, thereby permitting serial data to be transferred with respect to the memory cell array means via the data buses. The buffers are divided into n groups, n buffer selection circuits are each connected between a corresponding one of groups of the buffers and a corresponding one of the data buses, and the control unit supplies control signals to the buffer selection circuits, causing one of the buffers to be selectively connected to a corresponding one of the data buses via a corresponding one of the buffer selection circuits, and causing the data buses to be sequentially connected to the drivers via the data selection circuits, thereby permitting serial data to be transferred with respect to the memory cell array via the data buses.

Inventors

  • 👤 Takashi Ohsawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 18:42
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/10; G11C7/1015; G11C7/103; G11C7/1033; G11C7/1048

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 192 words
A semiconductor memory device comprising: at least one memory cell array means having N memory blocks; n buffer means for temporarily storing data to be transferred with respect to said memory means, respectively connected to said memory blocks and divided into n groups; n buffer selection means for selecting data transferred to and from said buffer means and each connected to a corresponding group of said buffer means; driver means; data selection means for selecting data transferred to and from said driver means; n data buses for transferring data between said n buffer selection means and said data selection means; and control means for supplying control signals to said buffer selection means and data selection means in each operation cycle, causing one of said buffer means belonging to a corresponding one of said groups of buffers to be selectively connected to a corresponding one of said data buses via a corresponding one of said buffer selection means, and causing said data buses to be sequentially connected to said driver means via said data selection means, thereby permitting serial data to be transferred with respect to said memory means via said data buses.
Claim 2
Dependent Claim 192 words
A semiconductor memory device comprising: at least one memory cell array means having N memory blocks; n buffer means for temporarily storing data to be transferred with respect to said memory means, respectively connected to said memory blocks and divided into n groups; n buffer selection means for selecting data transferred to and from said buffer means and each connected to a corresponding group of said buffer means; driver means; data selection means for selecting data transferred to and from said driver means; n data buses for transferring data between said n buffer selection means and said data selection means; and control means for supplying control signals to said buffer selection means and data selection means in each operation cycle, causing one of said buffer means belonging to a corresponding one of said groups of buffers to be selectively connected to a corresponding one of said data buses via a corresponding one of said buffer selection means, and causing said data buses to be sequentially connected to said driver means via said data selection means, thereby permitting serial data to be transferred with respect to said memory means via said data buses.
Claim 3
Dependent Claim 46 words
A semiconductor memory device according to claim 1, wherein said data selection means includes first and second data selection circuits each connected to said data buses, and said driver means includes first and second driver circuits respectively connected to said first and second data selection circuits.
Claim 4
Dependent Claim 20 words
A semiconductor memory device according to claim 2, wherein each of said data buses includes a pair of data lines.
Claim 5
Dependent Claim 19 words
A semiconductor memory device according to claim 2, wherein each of said data buses includes a single data line.
Claim 6
Dependent Claim 25 words
A semiconductor memory device according to claim 1, wherein said driver means includes first and second driver circuits commonly connected to said data selection means.
Claim 7
Dependent Claim 20 words
A semiconductor memory device according to claim 5, wherein each of said data buses includes a pair of data lines.
Claim 8
Dependent Claim 19 words
A semiconductor memory device according to claim 5, wherein each of said data buses includes a single data line.
Claim 9
Dependent Claim 52 words
A semiconductor memory device according to claim 1, wherein said memory cell array means includes M memory cell arrays each having N memory blocks, and said data selection means includes M data selection circuits respectively connected to said M memory cell arrays via said data buses, buffer selection means, and buffer means.

References Cited (Backward Citations)

US4562555A Cited
US4685088A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-01-31 1992-08-01 1993-01-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-01-31 1996-08-01 1997-01-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-01-31 2000-08-01 2001-01-31 $7700.00 Window Closed / Lapsed

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