Patent US5982220A successfully refreshed from Google Patents.
US5982220A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed multiplexer circuit
Assignee: MagnaChip Semiconductor Ltd
•
Filing: 1997-12-24
•
Granted: 1999-11-09
•
Expires: 2017-12-24
Abstract
Abstract A multiplexer circuit in which high speed operation and high integration can be achieved by distributing the parasitic capacitance generated in the common output stage of pass transistor. A multiplexer circuit which outputs any one of input signals of 1 to n, input to the n pass transistors after selecting it at the common output stage, in response to the the selection signal of 1 to n (n=a natural number), comprising; input means receiving 1 to i input signals (1<i<n); a first switching means which select any one of the input signals in response to the 1 to i selection signals and output it to a first common output stage; a second switching means which select any one of the i+1 to n input signals in response to the i+1 to n selection signals and output it to a second common output stage; and an output means which has input stage connected to the first common output stage and output stage connected to the second common output stage and outputs the final output signal to the external circuit.
Inventors
- 👤 Yong Byum Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:16
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/04; H03K17/041; H03K17/0416; H03K17/04163; H03K17/687; H03K17/693
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
168 words
A high speed multiplexer circuit which outputs any one of input signals of 1 to n, input to the n pass transistors after selecting it at the common output stage, in response to the selection signal of 1 to n (n=a natural number), comprising; input means receiving 0 to i input signals (0<i <n); a first switching means which selects any one of the input signals in response to the 1 to i selection signals and outputs a first output to a first common output stage; a second switching means which selects any one of the i+1 to n input signals in response to the i+1 to n selection signals and outputs a second output to a second common output state; and an output means including an input stage which receives the first output of the first common output stage and an output stage which receives the second output of the second common output stage, wherein the output means outputs a final output signal to the external circuit.
Claim 2
Dependent Claim
168 words
A high speed multiplexer circuit which outputs any one of input signals of 1 to n, input to the n pass transistors after selecting it at the common output stage, in response to the selection signal of 1 to n (n=a natural number), comprising; input means receiving 0 to i input signals (0<i <n); a first switching means which selects any one of the input signals in response to the 1 to i selection signals and outputs a first output to a first common output stage; a second switching means which selects any one of the i+1 to n input signals in response to the i+1 to n selection signals and outputs a second output to a second common output state; and an output means including an input stage which receives the first output of the first common output stage and an output stage which receives the second output of the second common output stage, wherein the output means outputs a final output signal to the external circuit.
Claim 3
Dependent Claim
27 words
The multiplexer circuit according to claim 1, wherein a speed of 1 to i input signals is higher than a speed of i+1 to n input signals.
Claim 4
Dependent Claim
26 words
The multiplexer circuit according to claim 1, wherein the input means comprise i inverter means which receive 1 to i input signals and output them respectively.
Claim 5
Dependent Claim
54 words
The multiplexer circuit according to claim 3, wherein the first switching means are composed of 1 to i pass transistors which receive the signals output from the 1 to i inverter means at their one ends, receive the 1 to i selection signals at their gates, and have common connection at their other ends.
Claim 6
Dependent Claim
54 words
The multiplexer circuit according to claim 1, wherein the second switching means are composed of i+1 to n pass transistors which receive the signals output from the i+1 to n inverter means at their one ends, receive the i+1 to n selection signals at their gates, and have common connection at their other ends.
Claim 7
Dependent Claim
50 words
The multiplexer circuit according to claim 1, wherein the output means is a latch circuit including two inverters, wherein an input of a first inverter is connected to an output of a second inverter and an input of the second inverter is connected to an output of the first inverter.
References Cited (Backward Citations)
US5815024A
Cited
US5436574A
Cited
US5648925A
Cited
US5835045A
Cited
US5543731A
Cited
US5654660A
Cited
US5578946A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |