Level shifted high impedance input multiplexor

Claim 2

A high input impedance CMOS multiplexor having a plurality of N-channel multiplexor input switching transistors connected to a common output node comprising: a main inverter having an input and an output; a weak inverter having an input connected to the output of the main inverter and the weak inverter having an output connected to the input of the main inverter; a buffer having an input connected to the common output node and the buffer having an output connected to the input of the main inverter; and the high input impedance of the CMOS multiplexor is approximately the high input impedance of the buffer when any signals are received by the plurality of N-channel multiplexor input switching transistors.

Claim 3

A high input impedance CMOS multiplexor as in claim 1 further comprising a turned-on isolation transistor wherein the output of the buffer is connected to the input of the main inverter through the isolation transistor in-order to isolate the buffer output from the output of the weak inverter.

Claim 4

A high input impedance CMOS multiplexor as in claim 2 further comprising: a power supply providing a voltage Vdd coupled to power the turned-on isolation transistor; a voltage source coupled to power the buffer and having voltage lower than the voltage Vdd powering the turned-on isolation transistor.

Claim 5

A high input impedance CMOS multiplexor as in claim 3 further comprising: an N-channel transistor having a drain and a gate electrode coupled to the voltage Vdd and a source electrode forming the voltage source, wherein the voltage source coupled to power the buffer is less than Vdd by approximately one threshold voltage drop of the N-channel transistor.

Claim 6

A high input impedance CMOS multiplexor having a plurality of N-channel multiplexor input switching transistors each having a signal input node and a select input for selectively coupling the signal input node to a common output node, the multiplexor comprising: a main inverter having an input and an output; a weak inverter having an input connected to the output of the main inverter and the weak inverter having an output connected to the input of the main inverter; an isolation transistor having an output connected to the input of the main inverter and the isolation transistor having a gate input connected to a first voltage source (Vdd) and the isolation transistor having an input; a buffer having an input connected to the common output node and the buffer having an output connected to the input of the isolation transistor, a second voltage source coupled to power the buffer, the second voltage source having a voltage less than Vdd by an amount approximately equal to a threshold voltage of the N-channel multiplexor input switching transistors so that the maximum voltage at the common output node substantially equals the voltage of the second voltage source in-order to shut off the buffer; and a pull up device coupled between the first voltage source and the common output node and controlled by each of the select inputs of the input switching transistors which operates to keep the common output node from floating in the event none of the plurality of N-channel multiplexor input switching transistors connected to the common output node are conducting current.

Claim 7

A high input impedance CMOS multiplexor having a plurality of N-channel multiplexor input switching transistors each having a signal input node and a select input for selectively coupling the signal input node to a common output node, the multiplexor comprising: a main inverter having an input and an output; a weak inverter having an input connected to the output of the main inverter and the weak inverter having an output connected to the input of the main inverter; an isolation transistor having an output connected to the input of the main inverter and the isolation transistor having a gate input connected to a first voltage source (Vdd) and the isolation transistor having an input; a buffer having an input connected to the common output node and the buffer having an output connected to the input of the isolation transistor, a second voltage source coupled to power the buffer, the second voltage source having a voltage less than Vdd by an amount approximately equal to a threshold voltage of the N-channel multiplexor input switching transistors so that the maximum voltage at the common output node substantially equals the voltage of the second voltage source in-order to shut off the buffer; and a pull up device coupled between the first voltage source and the common output node and controlled by each of the select inputs of the input switching transistors which operates to keep the common output node from floating in the event none of the plurality of N-channel multiplexor input switching transistors connected to the common output node are conducting current.

Claim 8

A high input impedance CMOS multiplexor as in claim 5 wherein: the pull up device includes a plurality of series connected transistors which are controlled by the select inputs.