Circuit arrangement for verifying data stored in a random access memory

Claim 2

A circuit arrangement for verifying data stored in a random access memory comprising, for each bit location of a column of the random access memory, input shift register means arranged to store an input data bit, multiplexer means arranged, during a write cycle, to write the input data bit into a bit position in the column of the random access memory, and during a verification cycle, arranged to write an inverse data bit into the bit position of the input data bit in column of the random access memory, and a comparator arranged to compare, after completion of the verification cycle, an output of the bit position in the random access memory with the inverse data bit and the result is stored in the input shift register means, wherein the multiplexer means comprises first and second transmission gates, wherein the first transmission gate is arranged to pass the input data bit to the bit location of the random access memory during a write cycle, and the second transmission gate in conjunction with an inverter connected to an input of the second transmission gate is arranged to pass the inverse data bit to a bit location of the random access memory during a verification cycle, wherein the inverter and second transmission gate act as a weak inverter circuit, and the weak inverter circuit is arranged so as not to overwrite a fully operational random access memory bit location, and wherein an input multiplexer is connected to an input of the input shift register, and is arranged to receive an input data bit, the result from the comparator and an input from a previous bit location.

Claim 3

A circuit arrangement as claimed in claim 1, wherein the comparator is a sense amplifier.

Claim 4

A verification circuit for a random access memory for writing data into a memory location and immediately verifying written data, the random access memory comprising: a random access memory cell including an input transistor having a first input, first output and a control electrode, an address control line coupled to the control electrode, a first inverter having a second input and second output, a second inverter having a third input coupled to the second output of the first inverter and a third output coupled to the second input of the first inverter and the first input of the input transistor, the second inverter being substantially weaker than the first inverter; wherein the verification circuit is connected to the first input of said input transistor, the verification circuit comprising: input register means having a fourth input, for receiving an input data bit, and a fourth output; a first multiplexer having connected between the fourth output of the input register means and the first input of said input transistor, the multiplexer having first and second paths, the second path including a third inverter for inverting a signal received from the input register means, the third inverter being of comparable strength to the second inverter, and a control means for selecting between the first and second paths; and comparison means coupled to the fourth output of the input register means and said random access memory cell for comparing signal values stored therein; whereby, in operation, write cycle data is written from said input register means via the first multiplexer path in the random access memory cell, and in a subsequent write verify cycle data is attempted to be written via the second multiplexer path into the memory cell, said comparison means detecting whether the write attempt is successful.

Claim 5

A verification circuit for a random access memory for writing data into a memory location and immediately verifying written data, the random access memory comprising: a random access memory cell including an input transistor having a first input, first output and a control electrode, an address control line coupled to the control electrode, a first inverter having a second input and second output, a second inverter having a third input coupled to the second output of the first inverter and a third output coupled to the second input of the first inverter and the first input of the input transistor, the second inverter being substantially weaker than the first inverter; wherein the verification circuit is connected to the first input of said input transistor, the verification circuit comprising: input register means having a fourth input, for receiving an input data bit, and a fourth output; a first multiplexer having connected between the fourth output of the input register means and the first input of said input transistor, the multiplexer having first and second paths, the second path including a third inverter for inverting a signal received from the input register means, the third inverter being of comparable strength to the second inverter, and a control means for selecting between the first and second paths; and comparison means coupled to the fourth output of the input register means and said random access memory cell for comparing signal values stored therein; whereby, in operation, write cycle data is written from said input register means via the first multiplexer path in the random access memory cell, and in a subsequent write verify cycle data is attempted to be written via the second multiplexer path into the memory cell, said comparison means detecting whether the write attempt is successful.

Claim 6

A circuit as claimed in claim 3, wherein the comparison means has an output, and a second multiplexer is coupled to receive an input data bit and an output of the comparison means, the second multiplexer having an output coupled to the input of the input register means, whereby in the write verify cycle the output of the comparison means is written into the input register means.