Method for testing mos memory store device

Claim 2

A process for testing cells of a semiconductor memory store comprising the steps of: a. placing a charge potential into all cells including a test cell of the store; b. placing a discharge potential into a disturb cell; c. waiting a period of time less than a refresh cycle of the store; d. toggling the potential placed in the test cell and the disturb cell to reverse potentials; e. waiting a period of time less than a refresh cycle for a possible charge migration to the test cell; and f. checking the test cell for a charge potential.

Claim 3

A process according to claim 1 wherein the steps a through f are repeated for the same test cell using a different disturb cell.

Claim 4

A process for testing cells of a semiconductor memory store comprising the steps of: a. addressing a test cell location; b. obtaining an address of a disturb cell from the test cell location addressed; c. placing a charge potential into all cells Of the store including the addressed test cell; d. addressing the disturb cell obtained; e. placing a discharge potential into the addressed disturb cell; f. waiting a period of time less than a refresh cycle of the store; g. placing a discharge potential into the addressed test cell; h. placing a charge potential into the addressed disturb cell; i. waiting a period of time less than a refresh cycle for a possible charge potential migration; and j. checking the test cell for a charge potential.

Claim 5

A process for testing cells of a semiconductor memory store comprising the steps of: a. addressing a test cell location; b. obtaining an address of a disturb cell from the test cell location addressed; c. placing a charge potential into all cells Of the store including the addressed test cell; d. addressing the disturb cell obtained; e. placing a discharge potential into the addressed disturb cell; f. waiting a period of time less than a refresh cycle of the store; g. placing a discharge potential into the addressed test cell; h. placing a charge potential into the addressed disturb cell; i. waiting a period of time less than a refresh cycle for a possible charge potential migration; and j. checking the test cell for a charge potential.

Claim 6

A process as defined by claim 3 further including the steps of: k. checking addressed disturb cell location for test cell being tested; l. repeating steps b-k until last disturb cell location is checked; and m. ending process after last disturb cell is checked.

Claim 7

A process for testing cells of a semiconductor memory store comprising the steps of: a. addressing a test cell location; b. obtaining an address of a disturb cell from the test cell location addressed; c. placing a charge potential into all cells of the store including the addressed test cell; d. addressing the disturb cell obtained; e. placing a discharge potential into the addressed disturb cell; f. reinstating the charge potential in the test cell; g. reinstating the discharge potential in the disturb cell; h. waiting a period of time less than a refresh cycle of the store; i. placing a discharge potential into the addressed test cell; j. placing a charge potential into the addressed disturb cell; k. waiting a period of time less than a refresh cycle for a possible charge potential migration; l. checking the test cell for a charge potential; m. checking addressed disturb cell location for test cell being tested; n. repeating steps b-m until last disturb cell location is checked; and o. ending process after last disturb cell is checked.

Claim 8

A process for testing cells of a semiconductor memory store comprising the steps of: a. addressing a test cell location; b. obtaining an address of a disturb cell from the test cell location addressed; c. placing a charge potential into all cells of the store including the addressed test cell; d. addressing the disturb cell obtained; e. placing a discharge potential into the addressed disturb cell; f. reinstating the charge potential in the test cell; g. reinstating the discharge potential in the disturb cell; h. waiting a period of time less than a refresh cycle of the store; i. placing a discharge potential into the addressed test cell; j. placing a charge potential into the addressed disturb cell; k. waiting a period of time less than a refresh cycle for a possible charge potential migration; l. checking the test cell for a charge potential; m. checking addressed disturb cell location for test cell being tested; n. repeating steps b-m until last disturb cell location is checked; and o. ending process after last disturb cell is checked.

Claim 9

A process of testing cells of a semiconductor memory store by using a data processing system, said process comprising the steps of: a. placing charge potential data information into a first register; b. transferring placed charge potential data information into all cells of the store from the first register; c. placing discharge potential data information into a second register; d. addressing a disturb cell selected; e. transferring placed discharge potential data information from the second register into the addressed disturb cell; f. waiting a period of time less than a refresh cycle of the store; g. transferring placed discharge potential data information from the second register into the addressed test cell; h. transferring placed charge potential data information from the first register into the addressed disturb cell; i. waiting a period of time less than a refresh cycle for a possible charge migration to the test cell; j. retrieving data information from the memory store; k. comparing data retrieved to data entered; l. going to step m if comparison is not obtained otherwise going to step n; m. indicating error occurrence; and n. ending process.

Claim 10

A process of testing cells of a semiconductor memory store by using a data processing system, said process comprising the steps of: a. placing charge potential data information into a first register; b. transferring placed charge potential data information into all cells of the store from the first register; c. placing discharge potential data information into a second register; d. addressing a disturb cell selected; e. transferring placed discharge potential data information from the second register into the addressed disturb cell; f. waiting a period of time less than a refresh cycle of the store; g. transferring placed discharge potential data information from the second register into the addressed test cell; h. transferring placed charge potential data information from the first register into the addressed disturb cell; i. waiting a period of time less than a refresh cycle for a possible charge migration to the test cell; j. retrieving data information from the memory store; k. comparing data retrieved to data entered; l. going to step m if comparison is not obtained otherwise going to step n; m. indicating error occurrence; and n. ending process.

Claim 11

A process as described in claim 6 wherein the steps d through n are repeated for the same test cell using a different disturb cell.

Claim 12

A process of testing cells of a semiconductor memory store by using a data processing system, said process comprising the steps of: a. transferring address of cell to be tested into a first register; b. selecting address of a disturb cell based on test cell address in first register; c. placing charge potential data information into a second register; d. transferring placed charge potential data information into all cells of the store from the second register; e. placing discharge potential data information into a third register; f. addressing the disturb cell selected; g. transferring placed discharge potential data information From the third register into the addressed disturb cell; h. waiting a period of time less than a refresh cycle of the store; i. transferring placed discharge potential data information from the third register into the addressed test cell; j. transferring placed charge potential data information from the second register into the addressed disturb cell; k. waiting a period of time less than a refresh cycle for a possible charge migration to the test cell; l. retrieving data information from the memory store; m. comparing data retrieved to data entered; n. going to step o if comparison is not obtained, otherwise going to step p; o. indicating error occurrence; and p. ending process.

Claim 13

A process of testing cells of a semiconductor memory store by using a data processing system, said process comprising the steps of: a. transferring address of cell to be tested into a first register; b. selecting address of a disturb cell based on test cell address in first register; c. placing charge potential data information into a second register; d. transferring placed charge potential data information into all cells of the store from the second register; e. placing discharge potential data information into a third register; f. addressing the disturb cell selected; g. transferring placed discharge potential data information From the third register into the addressed disturb cell; h. waiting a period of time less than a refresh cycle of the store; i. transferring placed discharge potential data information from the third register into the addressed test cell; j. transferring placed charge potential data information from the second register into the addressed disturb cell; k. waiting a period of time less than a refresh cycle for a possible charge migration to the test cell; l. retrieving data information from the memory store; m. comparing data retrieved to data entered; n. going to step o if comparison is not obtained, otherwise going to step p; o. indicating error occurrence; and p. ending process.

Claim 14

A process as defined by claim 8 wherein step n comprises going to step o if comparison is not obtained, otherwise going to step q: q. checking addressed disturb cell location; and r. going to step p if last disturb cell is indicated, otherwise going to step b.

Claim 15

In a data processing system, a process of testing cells of a semiconductor memory store comprising the steps of: a. transferring address of cell to be tested into a first register; b. selecting address of a disturb cell based on test cell address in first register; c. placing charge potential data information into a second register; d. transferring placed charge potential data information into all cells of the store from the second register; e. placing discharge potential data information into a third register; f. addressing the disturb cell selected; g. transferring placed discharge potential data information from the third register into the addressed disturb cell; h. addressing the test cell selected; i. transferring placed charge potential data information from the second register into the addressed test cell; j. addressing the disturb cell selected; k. transferring placed discharge potential data information from the third register into the addressed disturb cell; l. placing a first delay time information into a timer register; m. decrementing the information placed in the timer register; n. going to step o if timer register is equal to zero otherwise returning to step m; o. transferring placed discharge potential data information from the third register into the addressed test cell; p. transferring placed charge potential data information from the second register into the addressed disturb cell; q. placing a second delay time information into the timer register; r. decrementing the information placed in the timer register; s. going to step t if timer register is equal to zero otherwise returning to setp r; t. retrieving data information from the memory store; u. checking for a parity error on retrieved data information; v. going to step aa if an error is indicated, otherwise going to step w; w. comparing data retrieved to data entered; x. going to step aa if comparison is not obtained, otherwise going to step y; y. checking addressed disturb cell location; z. going to step bb if last disturb cell is indicated, otherwise going to step b; aa. indicating error occurrence; and bb. ending process.

Claim 16

In a data processing system, a process of testing cells of a semiconductor memory store comprising the steps of: a. transferring address of cell to be tested into a first register; b. selecting address of a disturb cell based on test cell address in first register; c. placing charge potential data information into a second register; d. transferring placed charge potential data information into all cells of the store from the second register; e. placing discharge potential data information into a third register; f. addressing the disturb cell selected; g. transferring placed discharge potential data information from the third register into the addressed disturb cell; h. addressing the test cell selected; i. transferring placed charge potential data information from the second register into the addressed test cell; j. addressing the disturb cell selected; k. transferring placed discharge potential data information from the third register into the addressed disturb cell; l. placing a first delay time information into a timer register; m. decrementing the information placed in the timer register; n. going to step o if timer register is equal to zero otherwise returning to step m; o. transferring placed discharge potential data information from the third register into the addressed test cell; p. transferring placed charge potential data information from the second register into the addressed disturb cell; q. placing a second delay time information into the timer register; r. decrementing the information placed in the timer register; s. going to step t if timer register is equal to zero otherwise returning to setp r; t. retrieving data information from the memory store; u. checking for a parity error on retrieved data information; v. going to step aa if an error is indicated, otherwise going to step w; w. comparing data retrieved to data entered; x. going to step aa if comparison is not obtained, otherwise going to step y; y. checking addressed disturb cell location; z. going to step bb if last disturb cell is indicated, otherwise going to step b; aa. indicating error occurrence; and bb. ending process.