Auxiliary test circuit for semiconductor storage device

Abstract

Abstract PURPOSE:To simplify a test pattern for fixing a compared result at a constant value and comparing the value with a response result by inputting an input sequence repeating '1' and '0' to a prescribed address, inputting the output data of adjacent 2 bits in the serial data to a comparator and comparing these inputs. CONSTITUTION:The values of scanning registers SRbn, SRb(n-1) of a scanning path through a parallel output terminal 5b are set as two input parts. Test data '0101-01' or '1010-10' are inputted to a RAM 8 through a scanning path 7a, its response result is obtained again in the scanning path 7a and then the response result of the RAM 8 is transferred while shifting the result every bit in the scanning registers SRb(n-1), SRbn in the scanning path 7b. When the RAM 8 is normal, two input parts of an exclusive OR gate 10 become '0' and '1' without fail, so that the value of an output terminal 11 is fixed on '1'. Consequently, the test pattern can be simplified.

Inventors

• 👤 Hideshi Maeno
• 👤 秀史 前野

Bibliographic Details