EP0637132A2
Expired / Lapsed
EP
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Simple temporary information storage circuit controllable with enable/reset signal
Assignee: NEC Corp
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Filing: 1994-07-29
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Granted: —
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Expires: 2014-07-29
Abstract
Abstract Only a flip flop circuit (11a), an n-channel enhancement type transfer transistor (Qn11) coupled between an input node and the flip flop (11a) and a p-channel enhancement type reset transistor (Qp12) coupled between a power voltage line (Vcc) and the flip flop circuit (11a) form in combination a temporary information storage circuit, and the n-channel enhancement type transfer transistor (Qn11) and the p-channel enhancement type reset transistor (Qp12) are respectively controlled by a latch control signal (CTL2) and an enable/reset signal (EBL2) for changing the status of the flip flop circuit.
Inventors
- 👤 Yutaka C/O Nec Corporation Hirata
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 16:23
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/06; G11C8/10; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
194 words
A temporary information storage circuit comprising: a) a latch circuit (11) responsive to a first control signal (CTL2) for storing a piece of information; and b) a reset circuit (12) responsive to a second control signal (EBL2) for changing said latch circuit between enabled state and reset state, characterized in that said latch circuit (11) comprises a transfer transistor (Qn11) responsive to said first control signal so as to provide a signal path for an input signal (Din) indicative of said piece of information, and a bistable circuit (11a) having an input node (N11) coupled to said transfer transistor (Qn11) and responsive to said input signal for changing an output signal (OUT2) thereof, and in that said reset circuit (12) is implemented by a switching transistor (Qp12) coupled between a source of constant voltage (Vcc) and said input node (N11) of said bistable circuit (11a) and responsive to said second control signal (EBL2) so that said bistable circuit (11a) forcibly changes said output signal (OUT2) to a certain level corresponding to said piece of information in said enabled state and to a reset level regardless of said piece of information in said reset state.
Claim 2
Dependent Claim
123 words
The temporary information data storage as set forth in claim 1, in which said bistable circuit (11a) is a flip flop circuit implemented by two inverters (IV11/IV12) having respective input nodes and respective output nodes, one of said input nodes and one of said output nodes being coupled to said input node (N11) of said bistable circuit, the other of said input nodes being coupled to the other of said output nodes where said output signal (OUT2) is produced, one of said two inverters (IV12) being smaller in current driving capability than a source (IV13) of said input signal and said transfer transistor (Qn11) so that said input signal can change the voltage level at said input node (N11) of said bistable circuit.
Claim 3
Dependent Claim
190 words
The temporary information storage circuit as set forth in claim 1, in which said temporary information storage circuit forms a part of an addressing system, said addressing system further comprising a plurality of address predecoder circuits (340-34i) for producing address predecoded signals (I0T/I0N - IiT/IiN) from address bits indicative of more than one addresses in a time division multiplexing fashion, a first address decoder unit (31a) coupled to said plurality of address predecoders for producing first address decoded signals, a plurality of first temporary information storage circuits (31b) each similar in circuit arrangement to said temporary information storage circuit (11/12), and responsive to said first and second control signals (CTLA2/EBLA2) in a first phase for temporarily storing said first address decoded signals, a second address decoder unit (32a) coupled to said plurality of address predecoders (340-34i) for producing second address decoded signal, and a plurality of second temporary information storage circuits (32b) each similar in circuit arrangement to said temporary information storage circuit (11/12), and responsive to said first and second control signals (CTLB2/EBLB2) in a second phase after said first phase for temporarily storing said second address decoded signals.
Claim 4
Dependent Claim
60 words
The temporary information storage circuit as set forth in claim 3, in which said addressing system further comprising a plurality of delayed latch circuits (410-41i) respectively associated with said plurality of address predecoder circuits (340-34i) for temporarily storing said address bits indicative of an address firstly supplied to said plurality of address predecoders (340-34i) in the time division multiplexing sequence.
References Cited (Backward Citations)
No citation records indexed.
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