Flip-flop circuit having transfer gate delay

Claim 1

An electronic flip-flop circuit having a data input, a data output and a clock signal input, and comprising a first transfer gate for transferring, under the control of the clock signal, data from he data input to an input of a first storage element, and a second transfer gate for transferring, under the control of the clock signal, data from an output of the first storage element to an input of a second storage element, an output of which constitutes the data output, the transfer gates being directly driven by the same clock signal, characterized in that the second transfer gate comprises means for prolonging the transfer time for data from the first to the second storage element, said means comprising a pMOS transistor and an nMOS transistor whose gates are connected to the output of the first storage element and whose drains are connected to the input of the second storage element, the source of the pMOS transistor being connected to the drain of a further pMOS transistor whose source is connected to a supply voltage and whose gate is connected to the clock signal, the source of the nMOS transistor being connected to the drain and the gate of a further nMOS transistor whose source is connected to the clock signal.