Finite metastable time synchronizer

Claim 2

A finite metastable time synchronizer for synchronizing an input data signal provided to a digital receiving circuit with a clock frequency of the receiving circuit, the synchronizer comprising; a master stage which receives the input data signal and is capable of providing two potential metastable points; and a slave stage capable of providing one potential metastable point and coupled to receive a master stage output via a data path which also serves as a feedforward/back path between the slave stage and the master stage to provide resolution of metastable conditions in the synchronizer.

Claim 3

A synchronizer as in claim 1 wherein the master stage comprises a Schmitt trigger and a cross-coupled inverter, such that the output of the Schmitt trigger is the input of the cross-coupled inverter.

Claim 4

A synchronizer as in claim 2 wherein the slave stage comprises a buffer inverter and a second cross-coupled inverter, such that the output of the buffer inverter is the input of the second cross-coupled inverter.

Claim 5

A synchronizer as in claim 3 wherein the w/L ratios of the transistors utilized in the Schmitt trigger are such that the Schmitt trigger dominates the second cross-coupled inverter.

Claim 6

A finite metastable time synchronizer for synchronizing an input data signal provided to a digital receiving circuit with a clock frequency of the receiving circuit, the synchronizer comprising: a. a first logic gate for receiving a data signal which is asynchronous to a clock signal and for providing an output signal upon receipt of the clock signal; b. a first stage which receives the output signal from the first logic gate and is capable of providing two potential metastable points; c. a second logic gate coupled to provide a data, feedforward/back path between the first stage and a second stage in response to the clock signal compliment; and d. a second stage coupled to receive a first stage output via the data path which also serves as a feedforward/back path between the second stage and the first stage to provide resolution of metastable conditions in the synchronizer.

Claim 7

A finite metastable time synchronizer for synchronizing an input data signal provided to a digital receiving circuit with a clock frequency of the receiving circuit, the synchronizer comprising: a. a first logic gate for receiving a data signal which is asynchronous to a clock signal and for providing an output signal upon receipt of the clock signal; b. a first stage which receives the output signal from the first logic gate and is capable of providing two potential metastable points; c. a second logic gate coupled to provide a data, feedforward/back path between the first stage and a second stage in response to the clock signal compliment; and d. a second stage coupled to receive a first stage output via the data path which also serves as a feedforward/back path between the second stage and the first stage to provide resolution of metastable conditions in the synchronizer.