US4667339A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Level sensitive latch stage
Assignee: International Business Machines Corp
•
Filing: 1983-12-05
•
Granted: 1987-05-19
•
Expires: 2003-12-05
Abstract
Abstract A logic circuit that has a plurality of stages that are driven by a clock source that provides at least 2 clock signals and includes at least a single latch stage located between two of the plurality of stages is configured with field effect transistor technology. The latch stage includes an isolation means for isolating the preceding circuit of the plurality of stages from flow-through of the clocks and signals that are connected to the latch stage, and a latch circuit for storing the data that is applied to the latch stage between clock pulses. A plurality of latch stages can easily be configured as a shift register latch.
Inventors
- 👤 Graham S. Tubbs
- 👤 Martin D. Daniels
- 👤 Robert Schaaf
- 👤 Ronald Walther
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:00
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
240 words
A logic circuit for storing of an input signal, having a plurality of stages of at least a first and second stage that are driven from a clock source means that provides a first and second clock signal with the second clock signal having a single phase, the second stage being configured with field effect transistors and the first stage having at least a shift output connected to the second stage, the second stage comprises: isolation means for electrically isolating the second stage from the first stage and for connecting the shift output to the second stage only when the first clock signal is present; the second stage includes a latch means and gate means between said isolation and latch means for providing a first logic signal on a shift terminal and a second logic signal on an output terminal in response to the second clock signal applied to said gate means; and the latch means includes, a first inverting amplifier having an input, and an output forming said shift terminal and a means for storing data and whose input is connected to the isolation means, a second inverting amplifier having an input and output and a means for storing data and whose input is connected to the output of the first inverting amplifier and whose output is the output terminal, and feedback path connecting the output of the second inverting amplifier to the input of the first inverting amplifier.
Claim 2
Dependent Claim
240 words
A logic circuit for storing of an input signal, having a plurality of stages of at least a first and second stage that are driven from a clock source means that provides a first and second clock signal with the second clock signal having a single phase, the second stage being configured with field effect transistors and the first stage having at least a shift output connected to the second stage, the second stage comprises: isolation means for electrically isolating the second stage from the first stage and for connecting the shift output to the second stage only when the first clock signal is present; the second stage includes a latch means and gate means between said isolation and latch means for providing a first logic signal on a shift terminal and a second logic signal on an output terminal in response to the second clock signal applied to said gate means; and the latch means includes, a first inverting amplifier having an input, and an output forming said shift terminal and a means for storing data and whose input is connected to the isolation means, a second inverting amplifier having an input and output and a means for storing data and whose input is connected to the output of the first inverting amplifier and whose output is the output terminal, and feedback path connecting the output of the second inverting amplifier to the input of the first inverting amplifier.
Claim 3
Dependent Claim
18 words
The logic circuit according to claim 1 further comprising: test circuit means for testing of the latch stage.
Claim 4
Dependent Claim
47 words
The logic circuit according to claim 2 wherein the test circuit includes: clock means for generating a test pulse; a gate input logic circuit means for gating the input signal with the test pulse; and output circuit means for sampling the logic state of the latch means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-18 | 1990-11-17 | 1991-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-18 | 1994-11-17 | 1995-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-18 | 1998-11-17 | 1999-05-19 | $7700.00 | Window Closed / Lapsed |