Master-slave flip-flop circuit

Claim 2

A logic circuit comprising a plurality of master-slave flip-flops, said master-slave flip-flops including master flip-flops and slave flip-flops having mutually complementary clock signals applied thereto, means for selectively producing a test signal, and means responsive to the test signal for placing, at the same time, the master flip-flops and slave flip-flops in an enable condition.

Claim 3

A logic circuit comprising a master flip-flop and a slave flip-flop, first means responsive to a first state of a clock signal for placing the master flip-flop in a first logic state, second means responsive to a second state of the clock signal, complementary to said first state, for placing the slave flip-flop in a second logic state, and third means responsive to the application of a test signal to the logic circuit for simultaneously placing the master flip-flop and the slave flip-flop in the first logic state irrespective of the state of the clock signal.

Claim 4

A logic circuit comprising a master flip-flop and a slave flip-flop, first means responsive to a first state of a clock signal for placing the master flip-flop in a first logic state, second means responsive to a second state of the clock signal, complementary to said first state, for placing the slave flip-flop in a second logic state, and third means responsive to the application of a test signal to the logic circuit for simultaneously placing the master flip-flop and the slave flip-flop in the first logic state irrespective of the state of the clock signal.

Claim 5

The logic circuit according to claim 2, wherein said master flip-flop and said slave flip-flop include a current switching circuit for inputting logic information, a flip-flop circuit for storing said logic information and means responsive to states of said clock signal for activating said current switching circuit and said flip-flop circuit.

Claim 6

The logic circuit according to claim 3, wherein said activating means includes current switching circuit means for selectively providing a current source with one of said current switching circuit and said flip-flop circuit.

Claim 7

A logic circuit comprising a master flip-flop including first and second nodes, first and second common nodes, a first transistor having a collector coupled to said first node, a base coupled to said second node and an emitter coupled to said first common node, a second transistor having a collector coupled to said second node, a base coupled to said first node and an emitter coupled to said first common node, a third transistor having a collector coupled to said first node, a base supplied with input information and an emitter coupled to said second common node, a fourth transistor having a collector coupled to said second node, a base supplied with a reference voltage and an emitter coupled to said second common node, first current source means, a fifth transistor having a collector coupled to said second common node and an emitter coupled to said first current source means, and a sixth transistor having a collector coupled to said first common node, a base supplied with a reference voltage and an emitter coupled to said first current source means, a slave flip-flop including third and fourth nodes, third and fourth common nodes, a seventh transistor having a collector coupled to said third node, a base coupled to said fourth node, and an emitter coupled to said third common node, a eighth transistor having a collector coupled to said fourth node, a base coupled to said third node, and an emitter coupled to said third common node, a ninth transistor having a collector coupled to said third node, a base supplied with a signal derived from said second node and an emitter coupled to said fourth common node, a tenth transistor having a collector coupled to said fourth node, a base supplied with a reference voltage and an emitter coupled to said fourth common node, second current source means, an eleventh transistor having a collector coupled to said fourth common node and an emitter coupled to said second current source means, and a twelfth transistor having a collector coupled to said third common node, a base supplied with a reference voltage and an emitter coupled to said second current source means, first means responsive to a first state of a clock signal for turning on said fifth transistor, second means responsive to a second state of the clock signal complementary to said first state for turning on said eleventh transistor and third means responsive to a test signal for turning on said fifth and eleventh transistors irrespective of said clock signal.

Claim 8

A logic circuit comprising a master flip-flop including first and second nodes, first and second common nodes, a first transistor having a collector coupled to said first node, a base coupled to said second node and an emitter coupled to said first common node, a second transistor having a collector coupled to said second node, a base coupled to said first node and an emitter coupled to said first common node, a third transistor having a collector coupled to said first node, a base supplied with input information and an emitter coupled to said second common node, a fourth transistor having a collector coupled to said second node, a base supplied with a reference voltage and an emitter coupled to said second common node, first current source means, a fifth transistor having a collector coupled to said second common node and an emitter coupled to said first current source means, and a sixth transistor having a collector coupled to said first common node, a base supplied with a reference voltage and an emitter coupled to said first current source means, a slave flip-flop including third and fourth nodes, third and fourth common nodes, a seventh transistor having a collector coupled to said third node, a base coupled to said fourth node, and an emitter coupled to said third common node, a eighth transistor having a collector coupled to said fourth node, a base coupled to said third node, and an emitter coupled to said third common node, a ninth transistor having a collector coupled to said third node, a base supplied with a signal derived from said second node and an emitter coupled to said fourth common node, a tenth transistor having a collector coupled to said fourth node, a base supplied with a reference voltage and an emitter coupled to said fourth common node, second current source means, an eleventh transistor having a collector coupled to said fourth common node and an emitter coupled to said second current source means, and a twelfth transistor having a collector coupled to said third common node, a base supplied with a reference voltage and an emitter coupled to said second current source means, first means responsive to a first state of a clock signal for turning on said fifth transistor, second means responsive to a second state of the clock signal complementary to said first state for turning on said eleventh transistor and third means responsive to a test signal for turning on said fifth and eleventh transistors irrespective of said clock signal.

Claim 9

The logic circuit according to claim 5, in which said third means includes first and second emitter-follower transistors for turning on said fifth and eleventh transistors respectively in response to said test signal.