Optimized operand formatting same

Claim 2

A digital operand formatting stage comprising: a first inverting means having a supply side, a ground side, an input and an output; a second inverting means having a supply side, a ground side, an input connected to the input of said first inverting means, and an output; a third inverting means having a supply side, a ground side, an input that is connected to the output of said second inverting means and an output that is connected to the output of said first inverting means; and, a general switching means for switching at least one of said first inverting means, said second inverting means and said third inverting means.

Claim 3

A digital operand formatting stage according to claim 1, wherein said general switching means comprises: a first switching means that is controlled by a first control signal for providing an electrical connection between a positive voltage supply and said supply side of said first inverting means; a second switching means that is controlled by a second control signal for providing an electrical connection between a negative voltage supply and said ground side of said first inverting means; and a third switching means that is controlled by said second control signal for providing an electrical connection between said positive voltage supply and said supply side of said third inverting means; a fourth switching means that is controlled by said first control signal for providing an electrical connection between said negative voltage supply and said ground side of said third inverting means.

Claim 4

A digital operand formatting stage according to claim 2, wherein at least one of said inverting means comprises a known CMOS inverter.

Claim 5

A digital operand formatting stage according to claim 2, wherein said first and third switching means each comprise at least one p-channel transistor.

Claim 6

A digital operand formatting stage according to claim 2, wherein said second and fourth switching means each comprise at least one n-channel transistor.

Claim 7

A digital operand formatting stage according to claim 2, wherein: said first inverting means comprises a known CMOS inverter; said second inverting means comprises a known CMOS inverter; said third inverting means comprises a known CMOS inverter; said first switching means comprises at least one p-channel transistor; said second switching means comprises at least one n-channel transistor; said third switching means comprises at least one p-channel transistor; and said fourth switching means comprises at least one n-channel transistor.

Claim 8

A digital formatting array comprising a plurality of digital operand formatting stages, each comprising: a first inverting means having a supply side, a ground side, an input and an output; a second inverting means having a supply side, a ground side, an input connected to the input of said first inverting means, and an output; a third inverting means having a supply side, a ground side, an input that is connected to the output of said second inverting means and an output that is connected to the output of said first inverting means to form an output of the digital operand formatting stage; and a switching means for switching at least one of said first inverting means, said second inverting means and said third inverting means, wherein said plurality of digital operand formatting stages are controlled independently of each other.

Claim 9

A digital formatting array comprising a plurality of digital operand formatting stages, each comprising: a first inverting means having a supply side, a ground side, an input and an output; a second inverting means having a supply side, a ground side, an input connected to the input of said first inverting means, and an output; a third inverting means having a supply side, a ground side, an input that is connected to the output of said second inverting means and an output that is connected to the output of said first inverting means to form an output of the digital operand formatting stage; and a switching means for switching at least one of said first inverting means, said second inverting means and said third inverting means, wherein said plurality of digital operand formatting stages are controlled independently of each other.

Claim 10

A digital operand formatting array according to claim 7 wherein the outputs of each of the plurality of digital operand formatting stages are connected to addend and augend inputs of a full adder such that said digital operand formatting array and said full adder together form a digital operand formatted adder.

Claim 11

A digital operand formatting array according to claim 7, wherein said switching means of each digital operand formatting stage comprises: a first switching means, controlled by a first control signal, for providing an electrical connection between a positive voltage supply and said supply side of said first inverting means; a second switching means, controlled by a second control signal, for providing an electrical connection between a negative voltage supply and said ground side of said first inverting means; a third switching means, controlled by said second control signal, for providing an electrical connection between said positive voltage supply and said supply side of said third inverting means; and a fourth switching means, controlled by said first control signal, for providing an electrical connection between said negative voltage supply and said ground side of said third inverting means, wherein the inputs of said first, second, third, and fourth switching means of each digital operand are connected in parallel with other inputs of another digital operand formatting stage of another formatting array of the same kind.