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US5973380A
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Semiconductor junction antifuse circuit
Assignee: Micron Technology Inc
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Filing: 1998-12-07
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Granted: 1999-10-26
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Expires: 2018-12-07
Abstract
Abstract An integrated semiconductor junction antifuse is formed from either adjacent regions of opposite doping types or spaced apart regions of similar doping type within a substrate. In its unblown state, the junction antifuse forms an open circuit that blocks current from flowing while in the blown state, the junction antifuse conducts current. The junction antifuse is blown by applying a breakdown voltage sufficient to overcome a semiconductor junction so that current flows across the reverse-biased semiconductor junction. As current flows across the reverse-biased junction, dopant migration forms a conductive path so that the junction antifuse no longer forms an open circuit.
Inventors
- 👤 Douglas J. Cutter
- 👤 Kurt D. Beigel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:10
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; G11C17/18; H; H10; H10B; H10B20/00; H10B20/20; H10B20/25
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
133 words
An integrated antifuse in an integrated circuit device, the integrated circuit including a plurality of integrated elements having respective semiconductor junctions, wherein substantially all of the semiconductor junctions have a breakdown voltage above a minimum breakdown voltage, comprising: a substrate of a first doping type having a well of a second doping type that is different from the first doping type; a first region of the first doping type formed in the well of the substrate; and a second region of the second doping type formed in the well of the substrate and adjacent the first region, the doping levels of the first and second regions being selected to form a junction having a breakdown voltage below a selected breakdown voltage, wherein the selected breakdown voltage is less than the minimum breakdown voltage.
Claim 2
Dependent Claim
133 words
An integrated antifuse in an integrated circuit device, the integrated circuit including a plurality of integrated elements having respective semiconductor junctions, wherein substantially all of the semiconductor junctions have a breakdown voltage above a minimum breakdown voltage, comprising: a substrate of a first doping type having a well of a second doping type that is different from the first doping type; a first region of the first doping type formed in the well of the substrate; and a second region of the second doping type formed in the well of the substrate and adjacent the first region, the doping levels of the first and second regions being selected to form a junction having a breakdown voltage below a selected breakdown voltage, wherein the selected breakdown voltage is less than the minimum breakdown voltage.
Claim 3
Dependent Claim
47 words
The antifuse of claim 1 wherein the antifuse includes a third region of the second doping type spaced apart from the second region of the second doping type with a portion of the first region of the first doping type positioned between the second and third regions.
Claim 4
Dependent Claim
169 words
An integrated antifuse in an integrated circuit device, the integrated circuit including a plurality of integrated elements having respective semiconductor junctions, wherein substantially all of the semiconductor junctions have a breakdown voltage above a minimum breakdown voltage, comprising: a substrate of a first doping type; a well of a second doping type different from the first doping type formed in the substrate; a first region of the first doping type formed in the well: a second region of a second doping type formed in the well adjacent the first region, the doping levels of the first and second regions being selected to form a junction having a breakdown voltage below a selected breakdown voltage, wherein the selected breakdown voltage is less than the minimum breakdown voltage; a third region of the first doping type formed in the well and spaced apart from the first region of the first doping type with a portion of the second region of the second doping type positioned between the first and third regions.
Claim 5
Dependent Claim
169 words
An integrated antifuse in an integrated circuit device, the integrated circuit including a plurality of integrated elements having respective semiconductor junctions, wherein substantially all of the semiconductor junctions have a breakdown voltage above a minimum breakdown voltage, comprising: a substrate of a first doping type; a well of a second doping type different from the first doping type formed in the substrate; a first region of the first doping type formed in the well: a second region of a second doping type formed in the well adjacent the first region, the doping levels of the first and second regions being selected to form a junction having a breakdown voltage below a selected breakdown voltage, wherein the selected breakdown voltage is less than the minimum breakdown voltage; a third region of the first doping type formed in the well and spaced apart from the first region of the first doping type with a portion of the second region of the second doping type positioned between the first and third regions.
Claim 6
Dependent Claim
51 words
An integrated circuit device, comprising: a first plurality of semiconductor junctions having a first breakdown voltage; and a second plurality of semiconductor junctions accessible for use as a fuse bank, the semiconductor junctions in the second plurality of semiconductor junctions having a second breakdown voltage lower than the first breakdown voltage.
Claim 7
Dependent Claim
51 words
An integrated circuit device, comprising: a first plurality of semiconductor junctions having a first breakdown voltage; and a second plurality of semiconductor junctions accessible for use as a fuse bank, the semiconductor junctions in the second plurality of semiconductor junctions having a second breakdown voltage lower than the first breakdown voltage.
Claim 8
Dependent Claim
24 words
The integrated circuit device of claim 4 wherein the second plurality of semiconductor junctions are coupled between a test node and a reference potential.
Claim 9
Dependent Claim
17 words
The integrated circuit device of claim 5, further including a precharge circuit coupled to the test node.
Claim 10
Dependent Claim
190 words
An integrated circuit package, comprising: an integrated device integrated into a substrate of a first doping type and having a plurality of integrated elements having respective semiconductor junctions, wherein substantially all of the semiconductor junctions have a breakdown voltage above a minimum breakdown voltage, the integrated device having a mode control input, the integrated device operating in a first operational mode in response to a first voltage at the mode select input and operating in a second mode in response to a second voltage at the mode select input; a biasing voltage terminal; and a semiconductor junction antifuse coupled between the biasing voltage and the mode select input, the junction antifuse including: a first region of the first doping type in the substrate; and a second region of a second doping type different from the first type in the substrate and adjacent the first region, the doping levels of the first and second regions being selected to form a junction having a breakdown voltage below the minimum breakdown voltage, the doping levels of the first and second regions being higher than substantially all other doping levels within the integrated device.
Claim 11
Dependent Claim
190 words
An integrated circuit package, comprising: an integrated device integrated into a substrate of a first doping type and having a plurality of integrated elements having respective semiconductor junctions, wherein substantially all of the semiconductor junctions have a breakdown voltage above a minimum breakdown voltage, the integrated device having a mode control input, the integrated device operating in a first operational mode in response to a first voltage at the mode select input and operating in a second mode in response to a second voltage at the mode select input; a biasing voltage terminal; and a semiconductor junction antifuse coupled between the biasing voltage and the mode select input, the junction antifuse including: a first region of the first doping type in the substrate; and a second region of a second doping type different from the first type in the substrate and adjacent the first region, the doping levels of the first and second regions being selected to form a junction having a breakdown voltage below the minimum breakdown voltage, the doping levels of the first and second regions being higher than substantially all other doping levels within the integrated device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-25 | 2003-04-26 | 2003-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-25 | 2007-04-26 | 2007-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-25 | 2011-04-26 | 2011-10-26 | $7700.00 | Window Closed / Lapsed |