US4287569A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
•
Filing: 1979-09-07
•
Granted: 1981-09-01
•
Expires: 1999-09-07
Abstract
Abstract In a semiconductor memory device having a plurality of memory cells located at a cross position of a plurality of bit lines and a plurality of word lines, the memory cell comprising a series circuit of an information storing element such as a diode or a fuse and a PNP type transistor. An N type epitaxial layer is used as a word line and the P type semiconductor substrate is used as a collector output line.
Inventors
- 👤 Toshitaka Fukushima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/617; G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H10B; H10B69/00; H10D88/00; Y; Y10; Y10S; Y10S257/00; Y10S257/926
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
185 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of word lines; a plurality of memory cells operatively connected to and located at a cross position of said plurality of bit lines and said plurality of word lines, wherein each of said memory cells comprises an information storing element having a first terminal and a PNP type transistor connected in series with said information storing element, wherein said PNP type transistor comprises a P type semiconductor substrate, having a surface, forming the collector region; an N type epitaxial layer, formed on the surface of said P type semiconductor substrate, forming the base region; and a P type region, formed in said N type epitaxial layer, forming the emitter region, wherein said first terminal of said information storing element is operatively connected to one of said plurality of bit lines, wherein the base region of said PNP type transistor is operatively connected to one of said plurality of word lines, and wherein the collectors of the PNP type transistor of each of said plurality of memory cells are operatively connected at a node.
Claim 2
Dependent Claim
185 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of word lines; a plurality of memory cells operatively connected to and located at a cross position of said plurality of bit lines and said plurality of word lines, wherein each of said memory cells comprises an information storing element having a first terminal and a PNP type transistor connected in series with said information storing element, wherein said PNP type transistor comprises a P type semiconductor substrate, having a surface, forming the collector region; an N type epitaxial layer, formed on the surface of said P type semiconductor substrate, forming the base region; and a P type region, formed in said N type epitaxial layer, forming the emitter region, wherein said first terminal of said information storing element is operatively connected to one of said plurality of bit lines, wherein the base region of said PNP type transistor is operatively connected to one of said plurality of word lines, and wherein the collectors of the PNP type transistor of each of said plurality of memory cells are operatively connected at a node.
Claim 3
Dependent Claim
20 words
A semiconductor memory device as set forth in claim 1, wherein said information storing element is a PN junction diode.
Claim 4
Dependent Claim
18 words
A semiconductor memory device as set forth in claim 1, wherein said information storing element is a fuse.
Claim 5
Dependent Claim
114 words
A semiconductor memory device having a plurality of PNP type transistors comprising: a P type semiconductor substrate having a surface; an N type epitaxial layer, having a surface, formed on the surface of said P type semiconductor substrate; a P type region formed on the surface of said N type epitaxial layer; an N + type region formed in said P type region; and a connecting conductor layer connected to said N + type region, wherein said connecting conductor layer is a bit line, wherein said N type epitaxial layer is a word line, and wherein said P type semiconductor substrate is a collector which is commmon to the plurality of PNP type transistors.
Claim 6
Dependent Claim
114 words
A semiconductor memory device having a plurality of PNP type transistors comprising: a P type semiconductor substrate having a surface; an N type epitaxial layer, having a surface, formed on the surface of said P type semiconductor substrate; a P type region formed on the surface of said N type epitaxial layer; an N + type region formed in said P type region; and a connecting conductor layer connected to said N + type region, wherein said connecting conductor layer is a bit line, wherein said N type epitaxial layer is a word line, and wherein said P type semiconductor substrate is a collector which is commmon to the plurality of PNP type transistors.
Claim 7
Dependent Claim
95 words
A semiconductor memory device comprising: a P type semiconductor substrate having a surface; an N type epitaxial layer, having a surface, formed on the surface of said P type semiconductor substrate; a P type region formed on the surface of said N type epitaxial layer; and a connecting conductor, forming a bit line; a fuse connected between said P type region and said connecting conductor, wherein said N type epitaxial layer is a word line and wherein said P type semiconductor substrate is a collector which is commmon to the plurality of PNP type transistors.
Claim 8
Dependent Claim
95 words
A semiconductor memory device comprising: a P type semiconductor substrate having a surface; an N type epitaxial layer, having a surface, formed on the surface of said P type semiconductor substrate; a P type region formed on the surface of said N type epitaxial layer; and a connecting conductor, forming a bit line; a fuse connected between said P type region and said connecting conductor, wherein said N type epitaxial layer is a word line and wherein said P type semiconductor substrate is a collector which is commmon to the plurality of PNP type transistors.
Claim 9
Dependent Claim
121 words
A semiconductor memory device having memory cells, comprising: a P type semiconductor substrate having a surface; an N type epitaxial layer former on the surface of said P type semiconductor substrate; a P type epitaxial layer, having a surface, formed on the surface of said N type epitaxial layer; a first isolation region, formed from the surface of said P type epitaxial layer to a predetermined depth in the N type epitaxial layer, for isolating the memory cells; and a second isolation region, formed from the surface of said P type epitaxial layer through said N type epitaxial layer to a predetermined depth in said P type semiconductor substrate, for defining a word line formed by said N type epitaxial layer.
Claim 10
Dependent Claim
121 words
A semiconductor memory device having memory cells, comprising: a P type semiconductor substrate having a surface; an N type epitaxial layer former on the surface of said P type semiconductor substrate; a P type epitaxial layer, having a surface, formed on the surface of said N type epitaxial layer; a first isolation region, formed from the surface of said P type epitaxial layer to a predetermined depth in the N type epitaxial layer, for isolating the memory cells; and a second isolation region, formed from the surface of said P type epitaxial layer through said N type epitaxial layer to a predetermined depth in said P type semiconductor substrate, for defining a word line formed by said N type epitaxial layer.
Claim 11
Dependent Claim
40 words
A semiconductor memory device as set forth in claim 1, 4 or 5, wherein an N + type layer is formed on the surface of said N type epitaxial layer along the direction of the sequence of the memory cells.
Claim 12
Dependent Claim
49 words
A semiconductor memory device as set forth in claim 1, 4, 5 or 6, wherein an N + layer is formed on the border between the surface of said P type semiconductor substrate and said N type epitaxial layer along the direction of the sequence of the memory cells.
Claim 13
Dependent Claim
19 words
A semiconductor device as set forth in claim 1, wherein said information storing element is a PN junction diode.
Claim 14
Dependent Claim
32 words
A semiconductor device as set forth in claim 9, wherein said PN junction diode comprises said P type region and a diode N + type layer formed in said P type region.
References Cited (Backward Citations)
US3529299A
Cited
US3611319A
Cited
US3742592A
Cited
US4131909A
Cited
US4112505A
Cited
US4064493A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-31 | 1985-03-02 | 1985-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-31 | 1989-03-02 | 1989-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-31 | 1993-03-02 | 1993-09-01 | $7700.00 | Window Closed / Lapsed |