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US5852323A Expired / Lapsed US ⏱️ 0.0 years remaining

Electrically programmable antifuse using metal penetration of a P-N junction

Assignee: Xilinx Inc
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Filing: 1997-01-16
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Granted: 1998-12-22
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Expires: 2017-01-16
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Abstract

Abstract An antifuse is described that can be formed without masks or mask steps beyond those required for a conventional CMOS process. The antifuse includes adjacent p-type and n-type diffusion regions that together form a P-N junction. The diffusion regions are tapered toward one another such that the P-N junction is located at a necked-down region of the antifuse. The diffusion regions are connected to respective terminals of a programming-voltage source via first and second metal electrical contacts, typically of aluminum metal. Each of the first and second electrical contacts includes a point directed toward the other of the first and second electrical contacts. The antifuse is programmed by providing a reverse-bias programming voltage across the electrical contacts. This programming voltage exceeds the breakdown voltage of the P-N junction so that current flows through the necked-down region of the antifuse between the points on the respective first and second electrical contacts. This current heats the region between the opposite points to create a hot filament between the first and second metal contacts. Metal from the metal contacts then diffuses along the filament to form a conductor between metal contacts.

Inventors

  • 👤 Robert O. Conn

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 02:04
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 115 words
An antifuse comprising: a first diffusion region of a first conductivity type formed in a semiconductor layer, the first diffusion region having a first width in a dimension parallel to the semiconductor layer; a second diffusion region of a second conductivity type formed in the semiconductor layer adjacent to the first diffusion region, the second diffusion region contacting the first diffusion region to form a P-N junction, the P-N junction having a second width in a dimension parallel to the semiconductor layer, wherein the second width is less than the first width; a first metal electrical contact formed on the first diffusion region; and a second metal electrical contact formed on the second diffusion region.
Claim 2
Dependent Claim 115 words
An antifuse comprising: a first diffusion region of a first conductivity type formed in a semiconductor layer, the first diffusion region having a first width in a dimension parallel to the semiconductor layer; a second diffusion region of a second conductivity type formed in the semiconductor layer adjacent to the first diffusion region, the second diffusion region contacting the first diffusion region to form a P-N junction, the P-N junction having a second width in a dimension parallel to the semiconductor layer, wherein the second width is less than the first width; a first metal electrical contact formed on the first diffusion region; and a second metal electrical contact formed on the second diffusion region.
Claim 3
Dependent Claim 26 words
The antifuse of claim 1, wherein the first and second electrical contacts define between them a path of least electrical resistance perpendicular to the P-N junction.
Claim 4
Dependent Claim 20 words
The antifuse of claim 2, the first metal electrical contact comprising a point directed toward the second metal electrical contact.
Claim 5
Dependent Claim 34 words
The antifuse of claim 3, the second metal electrical contact comprising a second point directed toward the first-mentioned point, wherein the first and second points define between them the path of least electrical resistance.
Claim 6
Dependent Claim 121 words
An antifuse comprising: a first diffusion region of a first conductivity type formed in a semiconductor layer; a second diffusion region of a second conductivity type formed in the semiconductor layer adjacent the first diffusion region, the second diffusion region contacting the first diffusion region to form a P-N junction; a first metal electrical contact formed on the first diffusion region and including a point directed toward the second diffusion region, the point defining a minimum distance between the first metal electrode and the second diffusion region, whereby the minimum distance defines a path of least electrical resistance between the first metal electrical contact and the second diffusion region; and a second metal electrical contact formed on the second diffusion region.
Claim 7
Dependent Claim 121 words
An antifuse comprising: a first diffusion region of a first conductivity type formed in a semiconductor layer; a second diffusion region of a second conductivity type formed in the semiconductor layer adjacent the first diffusion region, the second diffusion region contacting the first diffusion region to form a P-N junction; a first metal electrical contact formed on the first diffusion region and including a point directed toward the second diffusion region, the point defining a minimum distance between the first metal electrode and the second diffusion region, whereby the minimum distance defines a path of least electrical resistance between the first metal electrical contact and the second diffusion region; and a second metal electrical contact formed on the second diffusion region.
Claim 8
Dependent Claim 57 words
The antifuse of claim 5, wherein one of the first and second diffusion regions is tapered toward the other of the first and second diffusion regions to form a necked-down region in which the P-N junction is located, wherein the necked-down region includes a minimum width in a dimension parallel to a surface of the semiconductor layer.
Claim 9
Dependent Claim 60 words
The antifuse of claim 5, wherein one of the first and second diffusion regions is tapered toward the other of the first and second diffusion regions to form a necked-down region in which the P-N junction is located, and wherein the necked-down region has a width defined by the minimum feature size of a process used to form the antifuse.
Claim 10
Dependent Claim 15 words
The antifuse of claim 7, wherein the minimum feature size is less than one micron.
Claim 11
Dependent Claim 28 words
The antifuse of claim 6, wherein the first and second diffusion regions are tapered toward one another in a dimension parallel to a surface of the semiconductor layer.
Claim 12
Dependent Claim 34 words
The antifuse of claim 5, the second metal electrical contact comprising a second point directed toward the first-mentioned point, wherein the first and second points define between them the path of least electrical resistance.
Claim 13
Dependent Claim 36 words
The antifuse of claim 10, further comprising a means for generating a programming voltage, the means having a first terminal connected to the first electrical contact and a second terminal connected to the second electrical contact.
Claim 14
Dependent Claim 31 words
The antifuse of claim 11, wherein the programming voltage, when applied across the first and second electrical contacts, creates a filament of diffused metal between the first and second electrical contacts.
Claim 15
Dependent Claim 10 words
The antifuse of claim 5, wherein the metal is aluminum.
Claim 16
Dependent Claim 35 words
The antifuse of claim 5, wherein the semiconductor layer is of a first conductivity type and includes a well of a second conductivity type, and wherein the first diffusion region is formed within the well.
Claim 17
Dependent Claim 182 words
An antifuse comprising: a semiconductor layer of a first conductivity type, the layer including a well of a second conductivity type; a first diffusion region of the first conductivity type formed within the well; a second diffusion region of the second conductivity type formed within the layer and adjacent the first diffusion region, the second diffusion region contacting the first diffusion to form a P-N junction; a first metal electrical contact formed on the first diffusion region and including a point directed toward the second diffusion region, the point defining a minimum distance between the first metal electrode and the second diffusion region, whereby the minimum distance defines a path of least electrical resistance between the first metal electrical contact and the second diffusion region; a second metal electrical contact formed on the second diffusion region; and means for generating a programming voltage, the means having a first terminal connected to the first electrical contact and a second terminal connected to the second electrical contact, wherein the first metal electrical contact includes a point that extends toward the second metal electrical contact.
Claim 18
Dependent Claim 182 words
An antifuse comprising: a semiconductor layer of a first conductivity type, the layer including a well of a second conductivity type; a first diffusion region of the first conductivity type formed within the well; a second diffusion region of the second conductivity type formed within the layer and adjacent the first diffusion region, the second diffusion region contacting the first diffusion to form a P-N junction; a first metal electrical contact formed on the first diffusion region and including a point directed toward the second diffusion region, the point defining a minimum distance between the first metal electrode and the second diffusion region, whereby the minimum distance defines a path of least electrical resistance between the first metal electrical contact and the second diffusion region; a second metal electrical contact formed on the second diffusion region; and means for generating a programming voltage, the means having a first terminal connected to the first electrical contact and a second terminal connected to the second electrical contact, wherein the first metal electrical contact includes a point that extends toward the second metal electrical contact.

References Cited (Backward Citations)

US3641516A Cited
US4412308A Cited
US4683442A Cited
US5298784A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-12-21 2002-06-22 2002-12-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-12-21 2006-06-22 2006-12-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-12-21 2010-06-22 2010-12-22 $7700.00 Window Closed / Lapsed

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