US5818749A
Expired / Lapsed
US
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Integrated circuit memory device
Assignee: Micron Technology Inc
•
Filing: 1997-02-24
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Granted: 1998-10-06
•
Expires: 2017-02-24
Abstract
Abstract A memory array using structure changing memory elements in a reverse biased diode array is disclosed. A memory cell is programmed and read by reverse biasing the diode to overcome the diode's breakdown voltage. The disclosed reversed biased diode array exhibits much less substrate current leakage than a similar forward biased diode array.
Inventors
- 👤 Steven T. Harshfield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:33
CPC Classifications
G; G11; G11C; G11C13/00; G11C13/0002; G11C13/0004; G11C11/00; G11C11/56; G11C11/5678; G11C17/00; G11C17/14; G11C17/16; H; H10; H10B; H10B63/00; H10B63/10; G11C2213/00; G11C2213/70; G11C2213/72; H10D; H10D84/00; H10D84/80; H10D84/811
Claims Analysis
Total Claims: 56
Claim 1
Independent Claim
95 words
A memory cell for use in an integrated circuit memory device, said memory cell comprising: a memory element; and a diode having a breakdown voltage and being coupled to said memory element, said memory element being programmable in response to a programming voltage having a magnitude greater than said breakdown voltage being applied across said memory element and said diode, and said memory element being readable in response to a read voltage having a magnitude greater than said breakdown voltage and less than said programming voltage being applied across said memory element and said diode.
Claim 2
Dependent Claim
95 words
A memory cell for use in an integrated circuit memory device, said memory cell comprising: a memory element; and a diode having a breakdown voltage and being coupled to said memory element, said memory element being programmable in response to a programming voltage having a magnitude greater than said breakdown voltage being applied across said memory element and said diode, and said memory element being readable in response to a read voltage having a magnitude greater than said breakdown voltage and less than said programming voltage being applied across said memory element and said diode.
Claim 3
Dependent Claim
32 words
The memory cell, as set forth in claim 1, wherein said memory element comprises a material that changes from a first state to a second state in response to said programming voltage.
Claim 4
Dependent Claim
33 words
The memory cell, as set forth in claim 1, wherein said memory element comprises a chalcogenide material that changes from a first state to a second state in response to said programming voltage.
Claim 5
Dependent Claim
16 words
The memory cell, as set forth in claim 1, wherein said memory element comprises an antifuse.
Claim 6
Dependent Claim
16 words
The memory cell, as set forth in claim 1, wherein said diode comprises a zener diode.
Claim 7
Dependent Claim
16 words
The memory cell, as set forth in claim 1, wherein said diode comprises an avalanche diode.
Claim 8
Dependent Claim
40 words
The memory cell, as set forth in claim 1, wherein said programming voltage reverse-biases said diode and causes a current to flow through said diode and said memory element, said current having a magnitude sufficient to program said memory element.
Claim 9
Dependent Claim
40 words
The memory cell, as set forth in claim 1, wherein said read voltage reverse-biases said diode and causes a current to flow through said diode and said memory element, said current having a magnitude insufficient to program said memory element.
Claim 10
Dependent Claim
68 words
A memory cell for use in an integrated circuit memory device, said memory cell comprising: a memory element; and a diode coupled to said memory element for conducting a reverse current when said diode is reverse biased, said memory element being programmable in response to said reverse current having a first magnitude and said memory element being readable in response to said reverse current having a second magnitude.
Claim 11
Dependent Claim
68 words
A memory cell for use in an integrated circuit memory device, said memory cell comprising: a memory element; and a diode coupled to said memory element for conducting a reverse current when said diode is reverse biased, said memory element being programmable in response to said reverse current having a first magnitude and said memory element being readable in response to said reverse current having a second magnitude.
Claim 12
Dependent Claim
36 words
The memory cell, as set forth in claim 9, wherein said memory element comprises a material that changes from a first state to a second state in response to said reverse current having said first magnitude.
Claim 13
Dependent Claim
37 words
The memory cell, as set forth in claim 9, wherein said memory element comprises a chalcogenide material that changes from a first state to a second state in response to said reverse current having said first magnitude.
Claim 14
Dependent Claim
16 words
The memory cell, as set forth in claim 9, wherein said memory element comprises an antifuse.
Claim 15
Dependent Claim
16 words
The memory cell, as set forth in claim 9, wherein said diode comprises a zener diode.
Claim 16
Dependent Claim
16 words
The memory cell, as set forth in claim 9, wherein said diode comprises an avalanche diode.
Claim 17
Dependent Claim
103 words
A memory cell for use in an integrated circuit memory device, said memory cell comprising: a memory element; and a diode being coupled to said memory element, said memory element being programmable in response to a programming voltage being applied across said memory element and said diode, said programming voltage having a magnitude sufficient to reverse-bias said diode and to program said memory element, and said memory element being readable in response to a read voltage being applied across said memory element and said diode, said read voltage having a magnitude sufficient to reverse-bias said diode and insufficient to program said memory element.
Claim 18
Dependent Claim
103 words
A memory cell for use in an integrated circuit memory device, said memory cell comprising: a memory element; and a diode being coupled to said memory element, said memory element being programmable in response to a programming voltage being applied across said memory element and said diode, said programming voltage having a magnitude sufficient to reverse-bias said diode and to program said memory element, and said memory element being readable in response to a read voltage being applied across said memory element and said diode, said read voltage having a magnitude sufficient to reverse-bias said diode and insufficient to program said memory element.
Claim 19
Dependent Claim
32 words
The memory cell, as set forth in claim 15, wherein said memory element comprises a material that changes from a first state to a second state in response to said programming voltage.
Claim 20
Dependent Claim
33 words
The memory cell, as set forth in claim 15, wherein said memory element comprises a chalcogenide material that changes from a first state to a second state in response to said programming voltage.
Claim 21
Dependent Claim
16 words
The memory cell, as set forth in claim 15, wherein said memory element comprises an antifuse.
Claim 22
Dependent Claim
16 words
The memory cell, as set forth in claim 15, wherein said diode comprises a zener diode.
Claim 23
Dependent Claim
16 words
The memory cell, as set forth in claim 15, wherein said diode comprises an avalanche diode.
Claim 24
Dependent Claim
36 words
The memory cell, as set forth in claim 15, wherein said programming voltage causes a current to flow through said diode and said memory element, said current having a magnitude sufficient to program said memory element.
Claim 25
Dependent Claim
36 words
The memory cell, as set forth in claim 15, wherein said read voltage causes a current to flow through said diode and said memory element, said current having a magnitude insufficient to program said memory element.
Claim 26
Dependent Claim
226 words
An integrated circuit memory device comprising: an array of memory cells in a common well being arranged in rows and columns; a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together; and a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together; wherein each of said memory cells comprises: a memory element being coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode having a breakdown voltage and having an anode coupled to receive a voltage from said one of said plurality of column lines and having a cathode coupled to receive a voltage from said one of said plurality of row lines, said memory element being programmable in response to a programming voltage having a magnitude greater than said breakdown voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines, and said memory element being readable in response to a read voltage having a magnitude greater than said breakdown voltage and less than said programming voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines.
Claim 27
Dependent Claim
226 words
An integrated circuit memory device comprising: an array of memory cells in a common well being arranged in rows and columns; a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together; and a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together; wherein each of said memory cells comprises: a memory element being coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode having a breakdown voltage and having an anode coupled to receive a voltage from said one of said plurality of column lines and having a cathode coupled to receive a voltage from said one of said plurality of row lines, said memory element being programmable in response to a programming voltage having a magnitude greater than said breakdown voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines, and said memory element being readable in response to a read voltage having a magnitude greater than said breakdown voltage and less than said programming voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines.
Claim 28
Dependent Claim
32 words
The memory device, as set forth in claim 23, wherein said memory element comprises a material that changes from a first state to a second state in response to said programming voltage.
Claim 29
Dependent Claim
33 words
The memory device, as set forth in claim 23, wherein said memory element comprises a chalcogenide material that changes from a first state to a second state in response to said programming voltage.
Claim 30
Dependent Claim
16 words
The memory device, as set forth in claim 23, wherein said memory element comprises an antifuse.
Claim 31
Dependent Claim
16 words
The memory device, as set forth in claim 23, wherein said diode comprises a zener diode.
Claim 32
Dependent Claim
16 words
The memory device, as set forth in claim 23, wherein said diode comprises an avalanche diode.
Claim 33
Dependent Claim
40 words
The memory device, as set forth in claim 23, wherein said programming voltage reverse-biases said diode and causes a current to flow through said diode and said memory element, said current having a magnitude sufficient to program said memory element.
Claim 34
Dependent Claim
40 words
The memory device, as set forth in claim 23, wherein said read voltage reverse-biases said diode and causes a current to flow through said diode and said memory element, said current having a magnitude insufficient to program said memory element.
Claim 35
Dependent Claim
141 words
An integrated circuit memory device comprising: an array of memory cells in a common well being arranged in rows and columns; a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together; and a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together; wherein each of said memory cells comprises: a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode conducting a reverse current when said diode is reverse biased, said memory element being programmable in response to said reverse current having a first magnitude and said memory element being readable in response to said reverse current having a second magnitude.
Claim 36
Dependent Claim
141 words
An integrated circuit memory device comprising: an array of memory cells in a common well being arranged in rows and columns; a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together; and a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together; wherein each of said memory cells comprises: a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode conducting a reverse current when said diode is reverse biased, said memory element being programmable in response to said reverse current having a first magnitude and said memory element being readable in response to said reverse current having a second magnitude.
Claim 37
Dependent Claim
36 words
The memory device, as set forth in claim 31, wherein said memory element comprises a material that changes from a first state to a second state in response to said reverse current having said first magnitude.
Claim 38
Dependent Claim
37 words
The memory device, as set forth in claim 31, wherein said memory element comprises a chalcogenide material that changes from a first state to a second state in response to said reverse current having said first magnitude.
Claim 39
Dependent Claim
16 words
The memory device, as set forth in claim 31, wherein said memory element comprises an antifuse.
Claim 40
Dependent Claim
16 words
The memory device, as set forth in claim 31, wherein said diode comprises a zener diode.
Claim 41
Dependent Claim
16 words
The memory device, as set forth in claim 31, wherein said diode comprises an avalanche diode.
Claim 42
Dependent Claim
196 words
An integrated circuit memory device comprising: an array of memory cells in a common well being arranged in rows and columns; a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together; and a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together; wherein each of said memory cells comprises: a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said memory element being programmable in response to a programming voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines, said programming voltage having a magnitude sufficient to reverse-bias said diode and to program said memory element, and said memory element being readable in response to a read voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines, said read voltage having a magnitude sufficient to reverse-bias said diode and insufficient to program said memory element.
Claim 43
Dependent Claim
196 words
An integrated circuit memory device comprising: an array of memory cells in a common well being arranged in rows and columns; a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together; and a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together; wherein each of said memory cells comprises: a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said memory element being programmable in response to a programming voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines, said programming voltage having a magnitude sufficient to reverse-bias said diode and to program said memory element, and said memory element being readable in response to a read voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines, said read voltage having a magnitude sufficient to reverse-bias said diode and insufficient to program said memory element.
Claim 44
Dependent Claim
32 words
The memory device, as set forth in claim 37, wherein said memory element comprises a material that changes from a first state to a second state in response to said programming voltage.
Claim 45
Dependent Claim
33 words
The memory device, as set forth in claim 37, wherein said memory element comprises a chalcogenide material that changes from a first state to a second state in response to said programming voltage.
Claim 46
Dependent Claim
16 words
The memory device, as set forth in claim 37, wherein said memory element comprises an antifuse.
Claim 47
Dependent Claim
16 words
The memory device, as set forth in claim 37, wherein said diode comprises a zener diode.
Claim 48
Dependent Claim
16 words
The memory device, as set forth in claim 37, wherein said diode comprises an avalanche diode.
Claim 49
Dependent Claim
36 words
The memory device, as set forth in claim 37, wherein said programming voltage causes a current to flow through said diode and said memory element, said current having a magnitude sufficient to program said memory element.
Claim 50
Dependent Claim
36 words
The memory device, as set forth in claim 37, wherein said read voltage causes a current to flow through said diode and said memory element, said current having a magnitude insufficient to program said memory element.
Claim 51
Independent Claim
237 words
A method of operating an integrated circuit memory device, said memory device having an array of memory cells in a common well being arranged in rows and columns, a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together, a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together, wherein each of said memory cells comprises a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode having a breakdown voltage and having an anode coupled to receive a voltage from said one of said plurality of column lines and having a cathode coupled to receive a voltage from said one of said plurality of row lines, said method comprising the steps of: (a) programming said memory cell by applying a programming voltage between said one of said plurality of row lines and said one of said plurality of column lines, said programming voltage having a magnitude greater than said breakdown voltage; and (b) reading said memory cell by applying a read voltage between said one of said plurality of row lines and said one of said plurality of column lines, said read voltage having a magnitude greater than said breakdown voltage and less than said programming voltage.
Claim 52
Independent Claim
237 words
A method of operating an integrated circuit memory device, said memory device having an array of memory cells in a common well being arranged in rows and columns, a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together, a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together, wherein each of said memory cells comprises a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode having a breakdown voltage and having an anode coupled to receive a voltage from said one of said plurality of column lines and having a cathode coupled to receive a voltage from said one of said plurality of row lines, said method comprising the steps of: (a) programming said memory cell by applying a programming voltage between said one of said plurality of row lines and said one of said plurality of column lines, said programming voltage having a magnitude greater than said breakdown voltage; and (b) reading said memory cell by applying a read voltage between said one of said plurality of row lines and said one of said plurality of column lines, said read voltage having a magnitude greater than said breakdown voltage and less than said programming voltage.
Claim 53
Independent Claim
195 words
A method of operating an integrated circuit memory device, said memory device having an array of memory cells in a common well being arranged in rows and columns, a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together, a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together, wherein each of said memory cells comprises a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode conducting a reverse current when said diode is reverse biased, said method comprising the steps of: (a) programming said memory cell by applying a reverse current having a first magnitude through said memory cell from said one of said plurality of row lines to said one of said plurality of column lines; and (b) reading said memory cell by applying a reverse current having a second magnitude through said memory cell from said one of said plurality of row lines to said one of said plurality of column lines.
Claim 54
Independent Claim
195 words
A method of operating an integrated circuit memory device, said memory device having an array of memory cells in a common well being arranged in rows and columns, a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together, a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together, wherein each of said memory cells comprises a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode conducting a reverse current when said diode is reverse biased, said method comprising the steps of: (a) programming said memory cell by applying a reverse current having a first magnitude through said memory cell from said one of said plurality of row lines to said one of said plurality of column lines; and (b) reading said memory cell by applying a reverse current having a second magnitude through said memory cell from said one of said plurality of row lines to said one of said plurality of column lines.
Claim 55
Independent Claim
202 words
A method of operating an integrated circuit memory device, said memory device having an array of memory cells in a common well being arranged in rows and columns, a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together, a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together, wherein each of said memory cells comprises a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said method comprising the steps of: (a) programming said memory cell by applying a programming voltage between said one of said plurality of row lines and said one of said plurality of column lines, said programming voltage having a magnitude sufficient to reverse-bias said diode and to program said memory element; and (b) reading said memory cell by applying a read voltage between said one of said plurality of row lines and said one of said plurality of column lines, said read voltage having a magnitude sufficient to reverse-bias said diode and insufficient to program said memory element.
Claim 56
Independent Claim
202 words
A method of operating an integrated circuit memory device, said memory device having an array of memory cells in a common well being arranged in rows and columns, a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together, a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together, wherein each of said memory cells comprises a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said method comprising the steps of: (a) programming said memory cell by applying a programming voltage between said one of said plurality of row lines and said one of said plurality of column lines, said programming voltage having a magnitude sufficient to reverse-bias said diode and to program said memory element; and (b) reading said memory cell by applying a read voltage between said one of said plurality of row lines and said one of said plurality of column lines, said read voltage having a magnitude sufficient to reverse-bias said diode and insufficient to program said memory element.
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