Configuration control in a programmable logic device using non-volatile elements

Claim 1

A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising: a boundary scan test circuit including a number of external device pins, one of the external device pins being defined as a test data input pin, and at least one test data register which is defined as a configuration register; a set of serially connected configuration bit non-volatile element sense latches (CBSLs), the CBSLs storing a set of data of the non-volatile elements; means for processing the set of data of the non-volatile elements from the CBSLs to the configuration register when a first signal is applied; and means for processing a set of test data signals from the test data input pin to the configuration register when a second signal is applied.

Claim 2

A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising: a boundary scan test circuit including a number of external device pins, one of the external device pins being defined as a test data input pin, and at least one test data register which is defined as a configuration register; a set of serially connected configuration bit non-volatile element sense latches (CBSLs), the CBSLs storing a set of data of the non-volatile elements; means for processing the set of data of the non-volatile elements from the CBSLs to the configuration register when a first signal is applied; and means for processing a set of test data signals from the test data input pin to the configuration register when a second signal is applied.

Claim 9

A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising: a boundary scan test circuit that includes: a plurality of external device pins, one of the external device pins being defined as a test data input pin, at least one test data register which is defined as a configuration register, the test data input pin being coupled through a first transistor to the configuration register, the configuration register including a series of serially connected configuration latches and a configuration clock, and producing an output signal; a set of serially connected configuration bit non-volatile element sense latches (CBSLs) being coupled through a second transistor to the configuration register, the CBSLs storing a set of data of the non-volatile elements; means for processing the set of data of the non-volatile elements from the CBSLs to the configuration register when a first signal is applied to the second transistor; and means for processing a set of test data signals from the test data input pin to the configuration register when a second signal is applied to the first transistor.

Claim 10

A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising: a boundary scan test circuit that includes: a plurality of external device pins, one of the external device pins being defined as a test data input pin, at least one test data register which is defined as a configuration register, the test data input pin being coupled through a first transistor to the configuration register, the configuration register including a series of serially connected configuration latches and a configuration clock, and producing an output signal; a set of serially connected configuration bit non-volatile element sense latches (CBSLs) being coupled through a second transistor to the configuration register, the CBSLs storing a set of data of the non-volatile elements; means for processing the set of data of the non-volatile elements from the CBSLs to the configuration register when a first signal is applied to the second transistor; and means for processing a set of test data signals from the test data input pin to the configuration register when a second signal is applied to the first transistor.

Claim 15

A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising: a boundary scan test circuit that includes: one or more test data registers, at least one of the test data registers being defined as a configuration register; the configuration register producing an output signal and including a series of serially connected configuration latches and a configuration clock; a number of external device pins, one of the external device pins being defined as the test data input pin, the test data input pin being coupled through a first transistor to the configuration register; a test access port and a test access port controller; an instruction register; and a number of clocks and controls; a set of serially connected configuration bit non-volatile element sense latches (CBSLs) being coupled through a second transistor to the configuration register, the CBSLs storing a set of data of the non-volatile elements; means for processing the set of data of the non-volatile elements from the CBSLs to the configuration register upon the application of a first signal to a gate of the second transistor, the means including toggling the configuration clock for a number of cycles, the number of cycles being equal to a bit length of the configuration register; and means for processing a set of test data signals from the test data input pin to the configuration register when a second signal is applied to a gate of the first transistor.

Claim 16

A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising: a boundary scan test circuit that includes: one or more test data registers, at least one of the test data registers being defined as a configuration register; the configuration register producing an output signal and including a series of serially connected configuration latches and a configuration clock; a number of external device pins, one of the external device pins being defined as the test data input pin, the test data input pin being coupled through a first transistor to the configuration register; a test access port and a test access port controller; an instruction register; and a number of clocks and controls; a set of serially connected configuration bit non-volatile element sense latches (CBSLs) being coupled through a second transistor to the configuration register, the CBSLs storing a set of data of the non-volatile elements; means for processing the set of data of the non-volatile elements from the CBSLs to the configuration register upon the application of a first signal to a gate of the second transistor, the means including toggling the configuration clock for a number of cycles, the number of cycles being equal to a bit length of the configuration register; and means for processing a set of test data signals from the test data input pin to the configuration register when a second signal is applied to a gate of the first transistor.

Claim 19

A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising: a boundary scan test circuit including a number of external device pins, one of the external device pins being defined as a test data input pin, the test data input pin being coupled through a first transistor to a configuration register, the configuration register including a series of serially connected configuration latches, the series of configuration latches being connected in parallel to a series of configuration bit non-volatile elements; the configuration register including a clock and producing an output signal; and means for processing a set of test data signals from the test data input pin to the configuration register when an override signal is applied to the first transistor.

Claim 20

A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising: a boundary scan test circuit including a number of external device pins, one of the external device pins being defined as a test data input pin, the test data input pin being coupled through a first transistor to a configuration register, the configuration register including a series of serially connected configuration latches, the series of configuration latches being connected in parallel to a series of configuration bit non-volatile elements; the configuration register including a clock and producing an output signal; and means for processing a set of test data signals from the test data input pin to the configuration register when an override signal is applied to the first transistor.