Semiconductor device having a boundary scan test circuit

Claim 1

A semiconductor device comprising an internal logic circuit, a plurality of external pins and a boundary scan test circuit including a plurality of boundary scan register cells each disposed correspondingly to associated one of said external pins for transmitting parallel data between said internal logic circuit and said associated one of said external pins, said boundary scan register cells being electrically connected to each other responsive to an external signal to form a shift register for transmitting serial data, each of said boundary scan register cells comprising: a first selector having a first input for inputting said parallel data, a second input for inputting said serial data and a third input for inputting a code signal representing a bit of an ID code of said semiconductor device, said first selector selecting one of said parallel data, serial data and code signal in accordance with an input switching signal; a first register for latching an output signal from said first selector in response to a first latch signal; a second register for latching an output signal from said first register in response to a second latch signal; and a second selector for selecting said parallel data or an output signal from said second register in accordance with an output switching signal, an output signal from said first register of one of said boundary scan register cells constituting said serial data to be input to Succeeding one of said boundary scan register cells when said boundary scan register cells are connected to form said shift register.