US5347520A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Boundary-scan enable cell with non-critical enable path
Assignee: Intellectual Ventures I LLC
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Filing: 1991-09-18
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Granted: 1994-09-13
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Expires: 2011-09-18
Abstract
Abstract A boundary-scan enable cell which includes critical and non-critical enable paths without adding an extra layer of logic. The boundary-scan cell includes a multiplexer, a critical enable path which transmits critical enable terms coupled to a first multiplexer input, a sampling circuit which transmits non-critical terms coupled to a second multiplexer input, and a non-critical term path which transmits non-critical masking terms, coupled to the shift input of the multiplexer. Non-critical terms at the shift input are mimicked at the second input. Provision is also made for a test control circuit and a circuit for monitoring critical and non-critical terms.
Inventors
- 👤 David L. Simpson
- 👤 Wilson E. Smoak, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:00
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
235 words
A boundary-scan cell for testing a system logic and its pin connections comprising: a monitoring circuit including a NOR gate having critical enable term and non-critical term inputs and having a term output and a test output for comparison with a twin cell; a first multiplexer having critical enable term, non-critical term, and shift inputs; a sampling circuit coupled between the term output of the monitoring circuit and the non-critical term input of the first multiplexer including a second multiplexer having a term input and a previous cell contents input, a shift register coupled to the output of the second multiplexer including an inverter coupled to the output of the second multiplexer and a D-type flip-flop coupled to the output of the inverter, and a latch coupled between the output of the shift register and the non-critical term input of the first multiplexer; and a test control circuit including a first subcircuit coupled between the latch output and the non-critical term input of the first multiplexer including a first NAND gate having latch and first test inputs, a second NAND gate having first NAND gate and second test inputs, and a third NAND gate having second NAND gate and third test input and a non-critical term output, and a second subcircuit coupled between the system logic and the shift input of the first multiplexer including an OR gate having non-critical term and third test inputs.
Claim 2
Dependent Claim
235 words
A boundary-scan cell for testing a system logic and its pin connections comprising: a monitoring circuit including a NOR gate having critical enable term and non-critical term inputs and having a term output and a test output for comparison with a twin cell; a first multiplexer having critical enable term, non-critical term, and shift inputs; a sampling circuit coupled between the term output of the monitoring circuit and the non-critical term input of the first multiplexer including a second multiplexer having a term input and a previous cell contents input, a shift register coupled to the output of the second multiplexer including an inverter coupled to the output of the second multiplexer and a D-type flip-flop coupled to the output of the inverter, and a latch coupled between the output of the shift register and the non-critical term input of the first multiplexer; and a test control circuit including a first subcircuit coupled between the latch output and the non-critical term input of the first multiplexer including a first NAND gate having latch and first test inputs, a second NAND gate having first NAND gate and second test inputs, and a third NAND gate having second NAND gate and third test input and a non-critical term output, and a second subcircuit coupled between the system logic and the shift input of the first multiplexer including an OR gate having non-critical term and third test inputs.
Claim 3
Independent Claim
177 words
A device for isolating an input/output pad from an integrated circuit comprising: a monitoring circuit including a NOR gate having critical enable term and non-critical term inputs and having a term output and a test output for comparison with a twin cell; a first multiplexer having critical term, non-critical term, and shift inputs, the device selecting the critical term input during normal operation of the integrated circuit and the non-critical term input during both test and default operation of the integrated circuit; a sampling circuit coupled between the term output of the monitoring circuit and the non-critical term input of the first multiplexer including a second multiplexer having a term input and a previous device contents input, a shift register coupled to the output of the second multiplexer, and a latch coupled between the output of the shift register and the non-critical term input of the first multiplexer; and a test control circuit coupled between the integrated circuit and the shift inputs of the first multiplexer including an OR gate having non-critical term and third test inputs.
Claim 4
Independent Claim
177 words
A device for isolating an input/output pad from an integrated circuit comprising: a monitoring circuit including a NOR gate having critical enable term and non-critical term inputs and having a term output and a test output for comparison with a twin cell; a first multiplexer having critical term, non-critical term, and shift inputs, the device selecting the critical term input during normal operation of the integrated circuit and the non-critical term input during both test and default operation of the integrated circuit; a sampling circuit coupled between the term output of the monitoring circuit and the non-critical term input of the first multiplexer including a second multiplexer having a term input and a previous device contents input, a shift register coupled to the output of the second multiplexer, and a latch coupled between the output of the shift register and the non-critical term input of the first multiplexer; and a test control circuit coupled between the integrated circuit and the shift inputs of the first multiplexer including an OR gate having non-critical term and third test inputs.
Claim 5
Dependent Claim
72 words
The device as recited in claim 2, wherein the test control circuit further comprises: a first subcircuit coupled between the latch output and the non-critical term input of the first multiplexer including a first NAND gate having latch and first test inputs, a second NAND gate having first NAND gate and second test inputs, and a third NAND gate having second NAND gate and third test input and a non-critical term output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |