US5966731A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Protocol for communication with dynamic memory
Assignee: Rambus Inc
•
Filing: 1997-11-26
•
Granted: 1999-10-12
•
Expires: 2017-11-26
Abstract
Abstract A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.
Inventors
- 👤 Richard Maurice Barth
- 👤 Frederick Abbot Ware
- 👤 John Bradly Dillon
- 👤 Donald Charles Stark
- 👤 Craig Edward Hampel
- 👤 Matthew Murdy Griffin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:03
CPC Classifications
G; G06; G06F; G06F12/00; G11; G11C; G11C7/00; G11C7/22; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G11C5/00; G11C5/06; G11C5/066; G11C7/10; G11C7/1072; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
147 words
A method, for use by a memory controller coupled to a memory device over a bus, for deferring precharge decisions, the method comprising the steps of: transmitting a request packet to the memory device over a first number of lines of the bus, wherein the request packet specifies a data transfer operation; receiving requests for additional data transfer operations while the memory device is performing the data transfer operation; determining, based on the requests received for the additional transfer transactions, whether a precharge operation should be initiated after the data transfer operation; transmitting to the memory device over a second number of lines of the bus, at or about the end of the data transfer operation, a control signal that indicates whether a precharge operation should be initiated after the data transfer operation, wherein the second number of lines is less than the first number of lines.
Claim 2
Independent Claim
147 words
A method, for use by a memory controller coupled to a memory device over a bus, for deferring precharge decisions, the method comprising the steps of: transmitting a request packet to the memory device over a first number of lines of the bus, wherein the request packet specifies a data transfer operation; receiving requests for additional data transfer operations while the memory device is performing the data transfer operation; determining, based on the requests received for the additional transfer transactions, whether a precharge operation should be initiated after the data transfer operation; transmitting to the memory device over a second number of lines of the bus, at or about the end of the data transfer operation, a control signal that indicates whether a precharge operation should be initiated after the data transfer operation, wherein the second number of lines is less than the first number of lines.
Claim 3
Dependent Claim
47 words
The method of claim 1 wherein the step of transmitting the control signal is performed by transmitting a termination signal to the memory device, the memory device terminating the data transfer operation at a time that is based on when the memory device receives the termination signal.
Claim 4
Dependent Claim
121 words
The method of claim 2 wherein: the memory device is configured to terminate the data transfer operation after a particular data packet is transmitted if the memory device detects the termination signal on any one of a plurality of clock cycles; the memory controller indicates that a precharge operation is to be performed by transmitting the termination signal on a particular clock cycle of the plurality of clock cycles; the memory controller indicates that a precharge operation is not to be performed by transmitting the termination signal on a different clock cycle of the plurality of clock cycles; and the memory device initiates a precharge operation based the clock cycle on which the termination signal is detected by the memory device.
Claim 5
Dependent Claim
132 words
The method of claim 2 wherein: the memory device contains a plurality of banks; the memory device terminates the data transfer operation after a particular data packet is transmitted if the memory device detects the termination signal on any one of a plurality of clock cycles; the method further includes the step of establishing a correspondence between the plurality of clock cycles and the plurality of banks; the memory controller indicates a bank within the memory device on which a precharge operation is to be performed by transmitting the termination signal on the clock cycle of the plurality of clock cycles that corresponds to the bank; and the memory device initiates a precharge operation on the bank that corresponds to the clock cycle on which the memory device detects the termination signal.
Claim 6
Dependent Claim
145 words
A memory for storing data and performing data transfer operations, the memory comprising: a memory array integrated within the memory to store data; and a control circuitry integrated within the memory and coupled to a bus, the control circuitry configured to read control information carried on the bus, the control information including data that specifies a data transfer operation and a first address; the control circuitry configured to perform the specified data transfer operation on data stored in the memory beginning at the first address, the control circuitry configured to perform the specified data transfer operation on data stored beginning at additional locations specified in address information carried over the bus until detecting a terminate indication on the bus, the control circuitry configured to cease the data transfer operation at a time that is based on the time at which the terminate indication is detected.
Claim 7
Dependent Claim
145 words
A memory for storing data and performing data transfer operations, the memory comprising: a memory array integrated within the memory to store data; and a control circuitry integrated within the memory and coupled to a bus, the control circuitry configured to read control information carried on the bus, the control information including data that specifies a data transfer operation and a first address; the control circuitry configured to perform the specified data transfer operation on data stored in the memory beginning at the first address, the control circuitry configured to perform the specified data transfer operation on data stored beginning at additional locations specified in address information carried over the bus until detecting a terminate indication on the bus, the control circuitry configured to cease the data transfer operation at a time that is based on the time at which the terminate indication is detected.
Claim 8
Dependent Claim
58 words
The memory of claim 5, wherein the control circuitry is further configured to read address information carried on one or more lines of the bus while performing the specified data transfer operation using one or more other lines of the bus, and wherein the address information specifies where data involved in the specified data transfer operation is located.
Claim 9
Dependent Claim
44 words
The memory device of claim 5, wherein the control circuitry is further configured to detect a strobe signal on the bus and to begin performing the specified data transfer operation at a time based on the time at which the strobe signal is detected.
Claim 10
Dependent Claim
39 words
The memory device of claim 7 wherein the control information specifies a location of a first set of data, the control circuitry configured to retrieve the first set of data from the location prior to detecting the strobe signal.
Claim 11
Dependent Claim
83 words
The memory device of claim 8 wherein: the control circuitry is further configured to read address information from one or more lines of the bus, the address information specifies locations for one or more additional sets of data to be transmitted in the data transfer operation, the control circuitry retrieves the one or more additional sets of data upon reading the address information, and the control circuitry transmits the one or more additional sets of data after transmitting the first set of data.
Claim 12
Dependent Claim
106 words
A memory for storing data and performing data transfer operations, the memory comprising: an array to store memory data; and a control circuit integrated within the memory, the control circuit coupled to a bus and configured to read control information carried on the bus, the control information containing control data that specifies a data transfer operation and a first address of the memory data; the control circuit configured to perform the specified data transfer operation on the memory data beginning at the first address, the memory configured to terminate the data transfer operation at a time based on detection of a terminate indication on the bus.
Claim 13
Dependent Claim
106 words
A memory for storing data and performing data transfer operations, the memory comprising: an array to store memory data; and a control circuit integrated within the memory, the control circuit coupled to a bus and configured to read control information carried on the bus, the control information containing control data that specifies a data transfer operation and a first address of the memory data; the control circuit configured to perform the specified data transfer operation on the memory data beginning at the first address, the memory configured to terminate the data transfer operation at a time based on detection of a terminate indication on the bus.
Claim 14
Dependent Claim
42 words
The memory of claim 10, wherein the control circuit is further configured to detect a strobe signal on the bus and to begin performing the specified data transfer operation at a time based on detection of the strobe signal on the bus.
Claim 15
Dependent Claim
149 words
A memory for storing data and performing data transfer operations, the memory comprising: an array on a substrate to store memory data; and a control circuit on the substrate coupled to a bus, the control circuit configured to read control information carried on the bus, the control information containing control data that specifies a data transfer operation and a first address of the memory data and a location of a first set of data; the control circuit configured to perform the specified data transfer operation on the memory data beginning at the first address, the control circuit configured to detect a strobe signal on the bus and to begin performing the specified data transfer operation at a time based on detection of the strobe signal on the bus, the control circuit configured to retrieve the first set of data from the location prior to detection of the strobe signal.
Claim 16
Dependent Claim
149 words
A memory for storing data and performing data transfer operations, the memory comprising: an array on a substrate to store memory data; and a control circuit on the substrate coupled to a bus, the control circuit configured to read control information carried on the bus, the control information containing control data that specifies a data transfer operation and a first address of the memory data and a location of a first set of data; the control circuit configured to perform the specified data transfer operation on the memory data beginning at the first address, the control circuit configured to detect a strobe signal on the bus and to begin performing the specified data transfer operation at a time based on detection of the strobe signal on the bus, the control circuit configured to retrieve the first set of data from the location prior to detection of the strobe signal.
Claim 17
Dependent Claim
58 words
The memory of claim 12, wherein the control circuit is further configured to read address information carried on one or more lines of the bus while performing the specified data transfer operation using one or more other lines of the bus, and wherein the address information specifies where data involved in the specified data transfer operation is located.
Claim 18
Dependent Claim
13 words
The memory of claim 12, wherein the memory is contained within a package.
References Cited (Backward Citations)
GB2188759A
Cited
EP0339224A2
Cited
US5301278A
Cited
US5404327A
Cited
US5036493A
Cited
US5251178A
Cited
US5404463A
Cited
EP0535670A1
Cited
US5345573A
Cited
US5381538A
Cited
US5548786A
Cited
FR2695227A1
Cited
US5553248A
Cited
US5611058A
Cited
US5504874A
Cited
US5533204A
Cited
US5649161A
Cited
US5638531A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-11 | 2003-04-12 | 2003-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-11 | 2007-04-12 | 2007-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-11 | 2011-04-12 | 2011-10-12 | $7700.00 | Window Closed / Lapsed |