US5638531A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiprocessor integrated circuit with video refresh logic employing instruction/data caching and associated timing synchronization
Assignee: International Business Machines Corp
•
Filing: 1995-06-07
•
Granted: 1997-06-10
•
Expires: 2015-06-07
Abstract
Abstract A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Any graphics subsystem must be able to support a variety of video formats, causing video refresh logic to become complicated. Such potential complications are avoided by the provision of a simple, general purpose hardware refresh system based on the direct color graphics frame buffer, with the broader range of services being provided by emulation using one of the processors included in the device.
Inventors
- 👤 Dwayne T. Crump
- 👤 Steve T. Pancoast
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:36
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0875; G09; G09G; G09G5/00; G09G5/36; G09G5/363; G09G2340/00; G09G2340/02; G09G2360/00; G09G2360/12; G09G2360/121; G09G5/39; G09G5/395
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
259 words
An integrated circuit device comprising: a substrate, a plurality of identical processors formed on said substrate, each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit; a line bus formed on said substrate and interconnecting all of said plurality of processors for transferring data bit streams thereamong; a video input interface unit formed on said substrate and connected to said line bus for receiving an input signal stream; a video output interface unit formed on said substrate and connected to said line bus for delivering from the integrated circuit device an output video signal stream determined from processing by said plurality of processors, said video output interface unit having an output video data cache coupled to said line bus, an output FIFO register coupled to said output video data cache for receiving data delivered from said output video data cache, and synchronization circuitry for generating horizontal and vertical synchronization signals; a host interface unit formed on said substrate and connected to said line bus for exchanging with a host processor control signals effective for governing the function of said plurality of processors; a control bus formed on said substrate and interconnecting said host interface unit and said plurality of processors for exchange of control signals therewith apart from data bit streams transferred over said line bus; and a memory interface unit formed on said substrate and connected to said line bus for exchanging with memory elements data bit streams processed and to be processed by said plurality of processors.
Claim 2
Dependent Claim
259 words
An integrated circuit device comprising: a substrate, a plurality of identical processors formed on said substrate, each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit; a line bus formed on said substrate and interconnecting all of said plurality of processors for transferring data bit streams thereamong; a video input interface unit formed on said substrate and connected to said line bus for receiving an input signal stream; a video output interface unit formed on said substrate and connected to said line bus for delivering from the integrated circuit device an output video signal stream determined from processing by said plurality of processors, said video output interface unit having an output video data cache coupled to said line bus, an output FIFO register coupled to said output video data cache for receiving data delivered from said output video data cache, and synchronization circuitry for generating horizontal and vertical synchronization signals; a host interface unit formed on said substrate and connected to said line bus for exchanging with a host processor control signals effective for governing the function of said plurality of processors; a control bus formed on said substrate and interconnecting said host interface unit and said plurality of processors for exchange of control signals therewith apart from data bit streams transferred over said line bus; and a memory interface unit formed on said substrate and connected to said line bus for exchanging with memory elements data bit streams processed and to be processed by said plurality of processors.
Claim 3
Dependent Claim
51 words
An integrated circuit device according to claim 1 and further wherein said video output interface unit further comprises an address generator and sequencer circuit operatively coupled between said output video data cache and said output FIFO register for driving data from said output video data cache to said output FIFO register.
Claim 4
Dependent Claim
72 words
An integrated circuit device according to claim 1 and further wherein said video output interface unit further comprises a color space converter circuit operatively coupled between said output video data cache and said output FIFO register, said color space converter circuit and said output FIFO register being coupled to one of said processors and said one processor functioning for driving data from said output video data cache to said output FIFO register.
Claim 5
Independent Claim
348 words
A system for handling digital data and generating video display signals, the system comprising: a central processing unit; system random access memory for receiving and storing and delivering digital data; a bus interconnecting said central processing unit and said system random access memory for transferring digital data signals; and a video processor integrated circuit device operatively connected to said bus and thereby to said central processing unit and to said system random access memory, said video processor integrated circuit device processing video display signals under the direction of said central processing unit and having: a substrate, a plurality of identical processors formed on said substrate, each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit; a line bus formed on said substrate and interconnecting all of said plurality of processors for transferring data bit streams thereamong; a video input interface unit formed on said substrate and connected to said line bus for receiving an input signal stream; a video output interface unit formed on said substrate and connected to said line bus for delivering from the integrated circuit device an output video signal stream determined from processing by said plurality of processors, said video output interface unit having an output video data cache coupled to said line bus, an output FIFO register coupled to said output video data cache for receiving data delivered from said output video data cache, and synchronization circuitry for generating horizontal and vertical synchronization signals; a host interface unit formed on said substrate and connected to said line bus for exchanging with a host processor control signals effective for governing the function of said plurality of processors; a control bus formed on said substrate and interconnecting said host interface unit and said plurality of processors for exchange of control signals therewith apart from data bit streams transferred over said line bus; and a memory interface unit formed on said substrate and connected to said line bus for exchanging with memory elements data bit streams processed and to be processed by said plurality of processors.
Claim 6
Independent Claim
348 words
A system for handling digital data and generating video display signals, the system comprising: a central processing unit; system random access memory for receiving and storing and delivering digital data; a bus interconnecting said central processing unit and said system random access memory for transferring digital data signals; and a video processor integrated circuit device operatively connected to said bus and thereby to said central processing unit and to said system random access memory, said video processor integrated circuit device processing video display signals under the direction of said central processing unit and having: a substrate, a plurality of identical processors formed on said substrate, each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit; a line bus formed on said substrate and interconnecting all of said plurality of processors for transferring data bit streams thereamong; a video input interface unit formed on said substrate and connected to said line bus for receiving an input signal stream; a video output interface unit formed on said substrate and connected to said line bus for delivering from the integrated circuit device an output video signal stream determined from processing by said plurality of processors, said video output interface unit having an output video data cache coupled to said line bus, an output FIFO register coupled to said output video data cache for receiving data delivered from said output video data cache, and synchronization circuitry for generating horizontal and vertical synchronization signals; a host interface unit formed on said substrate and connected to said line bus for exchanging with a host processor control signals effective for governing the function of said plurality of processors; a control bus formed on said substrate and interconnecting said host interface unit and said plurality of processors for exchange of control signals therewith apart from data bit streams transferred over said line bus; and a memory interface unit formed on said substrate and connected to said line bus for exchanging with memory elements data bit streams processed and to be processed by said plurality of processors.
Claim 7
Dependent Claim
49 words
A system according to claim 4 and further wherein said video output interface unit further comprises an address generator and sequencer circuit operatively coupled between said output video data cache and said output FIFO register for driving data from said output video data cache to said output FIFO register.
Claim 8
Dependent Claim
70 words
A system according to claim 4 and further wherein said video output interface unit further comprises a color space converter circuit operatively coupled between said output video data cache and said output FIFO register, said color space converter circuit and said output FIFO register being coupled to one of said processors and said one processor functioning for driving data from said output video data cache to said output FIFO register.
References Cited (Backward Citations)
US5239654A
Cited
US5410649A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |