Memory controller

Claim 2

Method of operating a computing system which include at least two devices capable of making a plurality of different types of memory access requests to a plurality of memory banks, with some of said memory banks having a different speed of operation, with a memory controller responsive to said memory access requests for providing control signals to said memory banks which are indicative of sequences of operation of the memory banks, characterized by decoding a memory access request by the memory controller (110) to determine which one of the plurality of memory banks (120-123) is to be addressed; and providing said control signals from the memory controller to said one memory bank, with the duration of the cycle time of said control signals being dynamically determined as a function of one of the type of said one memory bank, and the source of the memory request.

Claim 3

Method of operating a computing system which includes a plurality of processors which are capable of making a plurality of different types of memory access requests to a plurality of different types of memory banks, with some of said memory bank having a different cycle time of operation, with a memory controller responsive to said memory access requests for provision of control signals to said memory banks which are indicative of sequences of operation of said memory banks, characterized by decoding a memory access request by the memory controller (110) to determine the row and column address of the selected memory bank (120 - 123) to be addressed; providing a row address strobe signal (RAS) and a column address strobe signal (CAS) by the memory controller to said selected memory bank for controlling the sequence of operation of said selected memory bank; and determining dynamically by said memory controller the row address strobe (RAS) precharge time and column address strobe (CAS) precharge time of said row address strobe signal (RAS) and column address strobe signal (CAS) as a function of one of the type of memory bank being accessed and the source of the memory access request.

Claim 4

Method of operating a computing system which includes a plurality of processors which are capable of making a plurality of different types of memory access requests to a plurality of different types of memory banks, with some of said memory bank having a different cycle time of operation, with a memory controller responsive to said memory access requests for provision of control signals to said memory banks which are indicative of sequences of operation of said memory banks, characterized by decoding a memory access request by the memory controller (110) to determine the row and column address of the selected memory bank (120 - 123) to be addressed; providing a row address strobe signal (RAS) and a column address strobe signal (CAS) by the memory controller to said selected memory bank for controlling the sequence of operation of said selected memory bank; and determining dynamically by said memory controller the row address strobe (RAS) precharge time and column address strobe (CAS) precharge time of said row address strobe signal (RAS) and column address strobe signal (CAS) as a function of one of the type of memory bank being accessed and the source of the memory access request.

Claim 5

Method of claim 2, characterized by determining the maximum time of a row address strobe (RAS) is active based on a maximum predetermined count which is a function of the system clock time.

Claim 6

Method of a claim 2, characterized by determining if the memory access request is a page mode request, and determining if the following memory access request is for the same page as the previous request, and if so concurrently processing such requests.

Claim 7

Method of claim 2, characterized by determining a row address strobe (RAS) access time and a column address strobe (CAS) access time of said row address strobe signal (RAS) and said column address strobe signal (CAS) as a function of one of the type of memory bank being accessed and the source of the memory access request.

Claim 8

Method of operating a computing system including a plurality of processors which are capable of making a plurality of different types of memory access requests to a plurality of memory banks which may have different cycle times, further including a memory controller responsive to said memory access requests for providing sequences of control signals to said memory banks which are indicative of sequences of operation for the memory banks, characterized by decoding a memory access request from a given one of the processors (100) by said memory controller (100) to determine the row and column and bank address of the selected memory bank (120 - 123); providing a row address strobe signal (RAS) by said memory controller; providing a column address strobe signal (CAS) by said memory controller; determining dynamically by said memory controller if extra column address strobe (CAS) access time for said column address strobe signal (CAS) is required as determined by one of the type of memory bank selected and the source of the memory access request; determining dynamically by said memory controller if extra column address strobe (CAS) precharge time for said column address strobe signal (CAS) is required as determined by one of the type of memory bank selected and the source of the memory access request; determining dynamically by said memory controller if extra row address strobe (RAS) precharge time for said row address strobe signal (RAS) is required as determined by one of the type of memory bank selected and the source of the memory access request; providing said row address strobe signal (RAS) with the determined precharge time to the selected memory bank; providing said a column address strobe signal (CAS) with the determined access time and precharge time to the selected memory bank; and providing said bank address signal to the selected memory bank, such that said selected memory bank may perform the sequences of operation controlled by said row address strobe signal (RAS) and said column address strobe signal (CAS).

Claim 9

Method of operating a computing system including a plurality of processors which are capable of making a plurality of different types of memory access requests to a plurality of memory banks which may have different cycle times, further including a memory controller responsive to said memory access requests for providing sequences of control signals to said memory banks which are indicative of sequences of operation for the memory banks, characterized by decoding a memory access request from a given one of the processors (100) by said memory controller (100) to determine the row and column and bank address of the selected memory bank (120 - 123); providing a row address strobe signal (RAS) by said memory controller; providing a column address strobe signal (CAS) by said memory controller; determining dynamically by said memory controller if extra column address strobe (CAS) access time for said column address strobe signal (CAS) is required as determined by one of the type of memory bank selected and the source of the memory access request; determining dynamically by said memory controller if extra column address strobe (CAS) precharge time for said column address strobe signal (CAS) is required as determined by one of the type of memory bank selected and the source of the memory access request; determining dynamically by said memory controller if extra row address strobe (RAS) precharge time for said row address strobe signal (RAS) is required as determined by one of the type of memory bank selected and the source of the memory access request; providing said row address strobe signal (RAS) with the determined precharge time to the selected memory bank; providing said a column address strobe signal (CAS) with the determined access time and precharge time to the selected memory bank; and providing said bank address signal to the selected memory bank, such that said selected memory bank may perform the sequences of operation controlled by said row address strobe signal (RAS) and said column address strobe signal (CAS).

Claim 10

Method of claims 1 to 6, characterized by memory access requests from at least two of said processors for provision of control signals to at least two of said memory banks which are indicative of different sequences of operation of said two memory banks, said method comprising the steps of: decoding said concurrent memory access requests from said two processors by said memory controller to determine the row and column address of each of the two selected memory banks to be addressed; providing a first and second row address strobe signal (RAS) and a first and second column address strobe signal (CAS) by said memory controller to each of the first and second selected memory banks, respectively, for controlling the sequence of operation of said first and second selected memory banks; and determining dynamically by said memory controller the different row address strobe (RAS) precharge time and column address strobe (CAS) precharge time of said first and second row address strobe signals (RAS), and said first and second column address strobe signals (CAS) as a function of one of the type of said first and second memory banks, respectively, being accessed and the source of the memory access request from the first and second processors, respectively.

Claim 11

Computing system, including at least two devices capable of making a plurality of different types of memory access requests, a plurality of memory banks which may have different speeds of operation, a memory controller, characterized by means (200) for decoding a memory access request from said at least two devices to determine which one of said memory banks (120 - 123)_is being addressed, and means (241) for providing control signals to the addressed memory bank (120 - 123), with the duration of the cycle time of said control signals being determined dynamically as a function of one of the speed of the addressed memory bank, and the source of the memory access request.

Claim 12

Computing system, including at least two devices capable of making a plurality of different types of memory access requests, a plurality of memory banks which may have different speeds of operation, a memory controller, characterized by means (200) for decoding a memory access request from said at least two devices to determine which one of said memory banks (120 - 123)_is being addressed, and means (241) for providing control signals to the addressed memory bank (120 - 123), with the duration of the cycle time of said control signals being determined dynamically as a function of one of the speed of the addressed memory bank, and the source of the memory access request.

Claim 13

Computing system, as set forth in claim 8 for operating with a method of one of claims 1 to 7, characterized by means for decoding a memory access request from one of the processors to determine which one of said memory banks is being addressed; means for providing a row address strobe signal (RAS) and column address strobe signal (CAS) to the memory bank being addressed to control the sequence of operation of the memory bank; and means for dynamically determining the row address strobe (RAS) precharge time and the column address strobe (CAS) precharge time of said row address strobe signal (RAS) and said column address strobe signal (CAS), respectively, as a function of one of the type of memory bank being accessed and the source of the memory access request.

Claim 14

Computing System as set forth in claim 8 or 9, characterized by a counter (210) which is incremented every clock cycle and compared to a maximum count based on the system clock for determining the maximum time row address strobe (RAS) is active.

Claim 15

Computing system as set forth in claims 8 or 9 or 10, characterized by means (200) for decoding a memory access request to a selected memory bank from a given one of said processors to determine the bank, row and column address of said given one of said processors, means for providing a row address strobe signal (RAS); means for providing a column address strobe signal (CAS); means for dynamically determining if extra column address strobe (CAS) access time for said column address strobe signal (CAS) is required as determined by one of the type of memory bank selected and the source of the memory access request; means for dynamically determining if extra column address strobe (CAS) precharge time for said column address strobe signal (CAS) signal is required as determined by one of the type of memory bank selected and the source of the memory access request; means for determining if extra row address strobe (RAS) precharge time for said row address strobe signal (RAS) is required as determined by one of the type of memory bank selected and the source of the memory access request; means for providing said row address strobe signal (RAS) with the determined precharge time to the selected memory bank; means for providing said column address strobe signal (CAS) with the determined access time and precharge time to the selected memory bank; and means for providing the decoded bank, row and column address signals to the selected memory bank, for enabling the selected memory bank to perform the sequences of operations controlled by said row address strobe signal (RAS) and said column address strobe signal (CAS).

Claim 16

Computing system, with a plurality of processors capable of making a plurality of different types of memory access requests; a plurality of memory banks which may have different cycle times of operation, characterized by means (200) for decoding on a prioritization basis a memory access request for a selected memory bank from a given one of said processors, for accessing the selected memory bank by said given one of said processors; means (304, 310) for providing input signals to said memory controller which are indicative of the type of memory bank selected and the source of the memory access request for modifying the cycle time of said control signals.

Claim 17

Computing system, with a plurality of processors capable of making a plurality of different types of memory access requests; a plurality of memory banks which may have different cycle times of operation, characterized by means (200) for decoding on a prioritization basis a memory access request for a selected memory bank from a given one of said processors, for accessing the selected memory bank by said given one of said processors; means (304, 310) for providing input signals to said memory controller which are indicative of the type of memory bank selected and the source of the memory access request for modifying the cycle time of said control signals.

Claim 18

Computing system, as set forth in one of claims 8 to 12, characterized by means for dynamically determining the differ­ent row address strobe (RAS) precharge time and the column address strobe (CAS) precharge time of said first and second row address strobe signals (RAS) and said first and second column address strobe signals (CAS), respectively, as a function of one of the type of said first and second memory banks, respectively, being accessed and the source of the memory access request from the first and second processors, respectively, and means for determining the different row address strobe (RAS) access time and a column address strobe (CAS) access time for said first and second row address strobe signals (RAS) and said first and second column address strobe signals (CAS), respectively, as a function of one of the type of said first and second memory banks, respectively, being accessed and the source of the memory access request from the first and second processors, respectively.