US5611058A
Expired / Lapsed
US
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System and method for transferring information between multiple buses
Assignee: International Business Machines Corp
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Filing: 1996-03-20
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Granted: 1997-03-11
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Expires: 2016-03-20
Abstract
Abstract A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred through a second bus between multiple second bus devices. Information is transferred through logic between the first and second buses. Using the logic, an action of a first bus device is enabled in response to a condition in which a second bus device waits for the action while the first bus device waits for a separate action on the second bus.
Inventors
- 👤 Charles R. Moore
- 👤 John S. Muhich
- 👤 Robert J. Reese
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:53
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F13/40; G06F13/4004; G06F13/4027
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
157 words
A system for transferring information between multiple buses, comprising: a first bus for transferring information between a plurality of first bus devices by completing multiple data phases in response to respective associated address phases, said data phases being ordered for completion in an order of said respective associated address phases; a second bus for transferring information between a plurality of second bus devices; and logic means coupled to said first and second buses for transferring information between said first and second buses and for enabling an action of a first bus device in response to a condition in which a second bus device waits for said action while said first bus device waits for a separate action on said second bus, wherein said action includes completing a particular one of said data phases before a preceding one of said ordered data phases, said preceding data phase being deferred by said first bus device pending said separate action.
Claim 2
Independent Claim
157 words
A system for transferring information between multiple buses, comprising: a first bus for transferring information between a plurality of first bus devices by completing multiple data phases in response to respective associated address phases, said data phases being ordered for completion in an order of said respective associated address phases; a second bus for transferring information between a plurality of second bus devices; and logic means coupled to said first and second buses for transferring information between said first and second buses and for enabling an action of a first bus device in response to a condition in which a second bus device waits for said action while said first bus device waits for a separate action on said second bus, wherein said action includes completing a particular one of said data phases before a preceding one of said ordered data phases, said preceding data phase being deferred by said first bus device pending said separate action.
Claim 3
Dependent Claim
35 words
The system of claim 1 wherein said plurality of first bus devices includes an input/output device, and wherein said action includes an output by said first bus device of particular information to said input/output device.
Claim 4
Dependent Claim
13 words
The system of claim 2 wherein said input/output device is a memory device.
Claim 5
Dependent Claim
28 words
The system of claim 3 wherein said action includes an output of said particular information from a cache memory of said first bus device to said memory device.
Claim 6
Dependent Claim
43 words
The system of claim 4 wherein said action is in response to said second bus device attempting to access said memory device while said particular information in said cache memory is in a modified state relative to associated information in said memory device.
Claim 7
Dependent Claim
29 words
The system of claim 1 wherein said logic means enables said action by enabling said first bus device to complete said particular data phase before said preceding data phase.
Claim 8
Dependent Claim
26 words
The system of claim 6 wherein said particular data phase is a write data phase, and wherein said preceding data phase is a read data phase.
Claim 9
Dependent Claim
20 words
The system of claim 1 wherein said second bus transfers information asynchronously relative to information transferred through said first bus.
Claim 10
Dependent Claim
23 words
The system of claim 1 wherein said separate action includes a release by said second bus device of control of said second bus.
Claim 11
Dependent Claim
40 words
The system of claim 1 wherein said plurality of first bus devices includes an input/output device integral with said first bus device, and wherein said action includes an output by said input/output device of particular information to said logic means.
Claim 12
Dependent Claim
41 words
The system of claim 1 wherein said plurality of second bus devices includes an input/output device integral with said second bus device, and wherein said separate action includes an output by said input/output device of particular information to said logic means.
Claim 13
Dependent Claim
94 words
Apparatus for processing information, comprising: means for connecting the apparatus to a bus and to a control line having multiple states; means for the apparatus to transfer information through said bus by completing multiple data phases in response to respective associated address phases, said data phases being ordered for completion in an order of said respective associated address phases; and means for the apparatus to selectively complete a particular one of said data phases before a preceding one of said ordered data phases in response to one of said states of said control line.
Claim 14
Dependent Claim
94 words
Apparatus for processing information, comprising: means for connecting the apparatus to a bus and to a control line having multiple states; means for the apparatus to transfer information through said bus by completing multiple data phases in response to respective associated address phases, said data phases being ordered for completion in an order of said respective associated address phases; and means for the apparatus to selectively complete a particular one of said data phases before a preceding one of said ordered data phases in response to one of said states of said control line.
Claim 15
Dependent Claim
26 words
The apparatus of claim 12 wherein said particular data phase is a write data phase, and wherein said preceding data phase is a read data phase.
Claim 16
Independent Claim
166 words
A method of transferring information between multiple buses, comprising the steps of: transferring information through a first bus between a plurality of first bus devices by completing multiple data phases in response to respective associated address phases, said data phases being ordered for completion in an order of said respective associated address phases; transferring information through a second bus between a plurality of second bus devices; transferring information through logic means between said first and second buses, said logic means being coupled to said first and second buses; and using said logic means, enabling an action of a first bus device in response to a condition in which a second bus device waits for said action while said first bus device waits for a separate action on said second bus, wherein said action includes completing a particular one of said data phases before a preceding one of said ordered data phases, said preceding data phase being deferred by said first bus device pending said separate action.
Claim 17
Independent Claim
166 words
A method of transferring information between multiple buses, comprising the steps of: transferring information through a first bus between a plurality of first bus devices by completing multiple data phases in response to respective associated address phases, said data phases being ordered for completion in an order of said respective associated address phases; transferring information through a second bus between a plurality of second bus devices; transferring information through logic means between said first and second buses, said logic means being coupled to said first and second buses; and using said logic means, enabling an action of a first bus device in response to a condition in which a second bus device waits for said action while said first bus device waits for a separate action on said second bus, wherein said action includes completing a particular one of said data phases before a preceding one of said ordered data phases, said preceding data phase being deferred by said first bus device pending said separate action.
Claim 18
Dependent Claim
35 words
The method of claim 14 wherein said enabling step comprises the step of enabling all output by said first bus device of particular information to an input/output device of said plurality of first bus devices.
Claim 19
Dependent Claim
30 words
The method of claim 15 wherein said enabling step comprises the step of enabling said output of particular information to said input/output device, said input/output device being a memory device.
Claim 20
Dependent Claim
32 words
The method of claim 16 wherein said enabling step comprises the step of enabling said output of particular information from a cache memory of said first bus device to said memory device.
Claim 21
Dependent Claim
50 words
The method of claim 17 wherein said enabling step comprises the step of enabling said output in response to said second bus device attempting to access said memory device while said particular information in said cache memory is in a modified state relative to associated information in said memory device.
Claim 22
Dependent Claim
48 words
The method of claim 14 wherein said enabling step comprises the step of enabling said first bus device to complete said particular data phase before said preceding data phase, said particular data phase being a write data phase, and said preceding data phase being a read data phase.
Claim 23
Dependent Claim
34 words
The method of claim 14 wherein said step of transferring information through said second bus comprises the step of transferring information through said second bus asynchronously relative to information transferred through said first bus.
Claim 24
Dependent Claim
42 words
The method of claim 14 wherein said enabling step comprises the step of enabling said action in response to said condition in which said first bus device waits for a release by said second bus device of control of said second bus.
Claim 25
Dependent Claim
45 words
The method of claim 14 wherein said enabling step comprises the step of enabling an output by an input/output device of particular information to said logic means, said input/output device being of said plurality of first bus devices and integral with said first bus device.
Claim 26
Dependent Claim
60 words
The method of claim 14 wherein said enabling step comprises the step of enabling said action in response to said condition in which said first bus device waits for an output by an input/output device of particular information to said logic means, said input/output device being of said plurality of second bus devices and integral with said second bus device.
References Cited (Backward Citations)
US4096571A
Cited
US4494193A
Cited
US4908749A
Cited
US4897787A
Cited
US4975838A
Cited
US4965723A
Cited
US5317715A
Cited
EP0344886A1
Cited
US5133074A
Cited
US5072369A
Cited
EP0392657A1
Cited
US5278974A
Cited
US5274763A
Cited
US5265216A
Cited
US5414820A
Cited
US5359715A
Cited
US5355455A
Cited
US5265211A
Cited
US5309567A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |