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US5965461A
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Controlled linewidth reduction during gate pattern formation using a spin-on barc
Assignee: Advanced Micro Devices Inc
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Filing: 1997-08-01
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Granted: 1999-10-12
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Expires: 2017-08-01
Abstract
Abstract A gate is formed by depositing a gate conductive layer over a substrate layer, depositing an organic spin-on bottom anti-reflective coating (BARC) over the gate conductive layer, and forming a resist mask on the BARC. Next, the resist mask is controllably etched to further reduce the critical dimensions of gate pattern formed therein, and then the gate is formed by etching the gate conductive layer using the reduced size resist mask.
Inventors
- 👤 Chih-Yuh Yang
- 👤 Scott A. Bell
- 👤 Daniel Steckert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:15
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/286; H10P50/287; H10P50/71; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/952
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
151 words
A method for forming a gate structure from a semiconductor wafer stack comprising a substrate and a conductive layer above the substrate, the method comprising: depositing an organic bottom anti-reflective coating (BARC) on the conductive layer; depositing a resist layer on the BARC; forming a first resist mask with the resist layer, wherein the first resist mask defines a first line having a first width; isotropically etching using a plasma comprised of HBr plus O 2 the first resist mask to create a second mask, such that portions of the first line are removed to form a second line having a second width, wherein the second width is narrower than the first width; etching through selected portions of the gate conductive layer as defined by the second resist mask to form a gate from the gate conductive layer, wherein the gate has a gate width substantially equal to the second width.
Claim 2
Independent Claim
151 words
A method for forming a gate structure from a semiconductor wafer stack comprising a substrate and a conductive layer above the substrate, the method comprising: depositing an organic bottom anti-reflective coating (BARC) on the conductive layer; depositing a resist layer on the BARC; forming a first resist mask with the resist layer, wherein the first resist mask defines a first line having a first width; isotropically etching using a plasma comprised of HBr plus O 2 the first resist mask to create a second mask, such that portions of the first line are removed to form a second line having a second width, wherein the second width is narrower than the first width; etching through selected portions of the gate conductive layer as defined by the second resist mask to form a gate from the gate conductive layer, wherein the gate has a gate width substantially equal to the second width.
Claim 3
Dependent Claim
17 words
The method as recited in claim 1, wherein the gate conductive layer includes a polycrystalline silicon layer.
Claim 4
Dependent Claim
23 words
The method as recited in claim 1, wherein the BARC is configured to attenuate interference waves produced in forming the first resist mask.
Claim 5
Dependent Claim
31 words
The method as recited in claim 3, wherein the first resist mask is formed using deep-UV wave forms and the BARC attenuates interference waves having an approximate wavelength of 248 nm.
Claim 6
Dependent Claim
32 words
The method as recited in claim 1, wherein the step of isotropically etching the first resist mask to create a second mask includes a trim etch process in a plasma etching system.
Claim 7
Dependent Claim
18 words
The method as recited in claim 5, wherein the plasma etching system is a reactive ion etching system.
Claim 8
Dependent Claim
39 words
The method as recited in claim 6, wherein a mixture of gases supplied to a reactor within the plasma etching system includes approximately 10 to 30 sccm of HBr and approximately 20 to 50 sccm of O 2 .
Claim 9
Dependent Claim
26 words
The method as recited in claim 7, wherein the mixture of gases includes approximately 15 sccm of HBr and approximately 45 sccm of O 2 .
Claim 10
Dependent Claim
31 words
The method as recited in claim 6, wherein a reactor within the reactive ion etching system is supplied with a biasing power of approximately 300 Watts, during the trim etch process.
Claim 11
Dependent Claim
31 words
The method as recited in claim 6, wherein a reactor within the reactive ion etching system has a pressure that is maintained at approximately 100 mT, during the trim etch process.
Claim 12
Dependent Claim
19 words
The method as recited in claim 1, further comprising removing the second resist mask and BARC from the gate.
Claim 13
Dependent Claim
19 words
The method as recited in claim 1, wherein the resist layer is a spin-on resist layer that comprises polymides.
Claim 14
Dependent Claim
19 words
The method as recited in claim 1, wherein the resist layer is a spin-on resist layer that comprises polysulfones.
Claim 15
Independent Claim
102 words
A method for forming a gate on a semiconductor wafer using a bottom anti-reflective coating and a trim etch process, the method comprising: creating a wafer stack by forming a gate conductive layer over a substrate, depositing an organic bottom anti-reflective coating (BARC), and forming a resist mask on the BARC; isotropically etching using a plasma comprised of HBr plus O 2 the resist mask and BARC to reduce a width of a gate line pattern formed in the resist mask; and shaping the wafer stack using the isotropically etched resist mask by etching through exposed portions of the gate conductive layer.
Claim 16
Independent Claim
102 words
A method for forming a gate on a semiconductor wafer using a bottom anti-reflective coating and a trim etch process, the method comprising: creating a wafer stack by forming a gate conductive layer over a substrate, depositing an organic bottom anti-reflective coating (BARC), and forming a resist mask on the BARC; isotropically etching using a plasma comprised of HBr plus O 2 the resist mask and BARC to reduce a width of a gate line pattern formed in the resist mask; and shaping the wafer stack using the isotropically etched resist mask by etching through exposed portions of the gate conductive layer.
Claim 17
Dependent Claim
20 words
The method as recited in claim 14, wherein the gate conductive layer includes a polycrystalline silicon layer, approximately 1,700Å thick.
Claim 18
Dependent Claim
31 words
The method as recited in claim 14, wherein the first resist mask is formed using deep-UV wave forms and the BARC attenuates interference waves having an approximate wavelength of 248 nm.
Claim 19
Dependent Claim
21 words
The method as recited in claim 14, wherein the ratio of HBr to O 2 is between approximately 1:2 and 1:3.
Claim 20
Dependent Claim
18 words
The method as recited in claim 14, further comprising removing the resist mask and BARC from the gate.
Claim 21
Dependent Claim
13 words
The method as recited in claim 14, wherein the resist mask comprises polymides.
Claim 22
Dependent Claim
13 words
The method as recited in claim 14, wherein the resist mask comprises polysulfones.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-11 | 2003-04-12 | 2003-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-11 | 2007-04-12 | 2007-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-11 | 2011-04-12 | 2011-10-12 | $7700.00 | Window Closed / Lapsed |