Patent US5963806A successfully refreshed from Google Patents.
US5963806A
Expired / Lapsed
US
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Method of forming memory cell with built-in erasure feature
Assignee: Promos Technologies Inc
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Filing: 1997-08-19
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Granted: 1999-10-05
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Expires: 2017-08-19
Abstract
Abstract A method of fabricating an E 2 PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.
Inventors
- 👤 Kuo-Tung Sung
- 👤 Wen-Ting Chu
- 👤 Huoy-Jong Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:26
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/6891; H10D30/6892; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
179 words
A process for fabricating a semiconductor memory device, comprising the steps of: forming a plurality of insulation regions on a semiconductor substrate to define at least one active region on the substrate; forming a first insulating layer on said active region; forming a patterned first silicon layer on a portion of said first insulating layer; forming a patterned second insulating layer overlying at least a portion of said first silicon layer; forming a recess in said first insulating layer underneath said first silicon layer by removing portions of said first insulating layer between said first silicon layer and said substrate, said recess exposing portions of said substrate and said first silicon layer; forming a patterned third insulating layer on said exposed portions of said substrate and said first silicon layer, said third insulating layer partially filling said recess; and forming a patterned second silicon layer covering at least a portion of said third insulating layer and further filling said recess, wherein said second silicon layer includes at least one of a sharp tip and a wedge filling said recess.
Claim 2
Dependent Claim
179 words
A process for fabricating a semiconductor memory device, comprising the steps of: forming a plurality of insulation regions on a semiconductor substrate to define at least one active region on the substrate; forming a first insulating layer on said active region; forming a patterned first silicon layer on a portion of said first insulating layer; forming a patterned second insulating layer overlying at least a portion of said first silicon layer; forming a recess in said first insulating layer underneath said first silicon layer by removing portions of said first insulating layer between said first silicon layer and said substrate, said recess exposing portions of said substrate and said first silicon layer; forming a patterned third insulating layer on said exposed portions of said substrate and said first silicon layer, said third insulating layer partially filling said recess; and forming a patterned second silicon layer covering at least a portion of said third insulating layer and further filling said recess, wherein said second silicon layer includes at least one of a sharp tip and a wedge filling said recess.
Claim 3
Dependent Claim
14 words
The process as in claim 1, wherein said first insulating layer is silicon dioxide.
Claim 4
Dependent Claim
18 words
The process as in claim 1, wherein said first insulating layer is approximately 5 to 50 nm thick.
Claim 5
Dependent Claim
18 words
The process as in claim 1, wherein said first silicon layer is approximately 50 to 500 nm thick.
Claim 6
Dependent Claim
14 words
The process as in claim 1, wherein said first silicon layer is polycrystalline silicon.
Claim 7
Dependent Claim
14 words
The process as in claim 1, wherein said second insulating layer is silicon dioxide.
Claim 8
Dependent Claim
18 words
The process as in claim 6, wherein said silicon dioxide layer is approximately 5 to 200 nm thick.
Claim 9
Dependent Claim
14 words
The process as in claim 1, wherein said recess is formed by isotropic etching.
Claim 10
Dependent Claim
18 words
The process as in claim 1, wherein said second silicon layer is approximately 30 to 500 nm thick.
Claim 11
Dependent Claim
44 words
The process as in claim 1, further comprising the steps of: forming a patterned fourth insulating layer on at least a portion of said second silicon layer; and forming a patterned third silicon layer on at least a portion of said fourth insulating layer.
Claim 12
Dependent Claim
14 words
The process as in claim 10, wherein said first insulating layer is silicon dioxide.
Claim 13
Dependent Claim
18 words
The process as in claim 10, wherein said first insulating layer is approximately 5 to 50 nm thick.
Claim 14
Dependent Claim
18 words
The process as in claim 10, wherein said first silicon layer is approximately 50 to 500 nm thick.
Claim 15
Dependent Claim
14 words
The process as in claim 10, wherein said first silicon layer is polycrystalline silicon.
Claim 16
Dependent Claim
14 words
The process as in claim 10, wherein said second insulating layer is silicon dioxide.
Claim 17
Dependent Claim
18 words
The process as in claim 15, wherein said second insulating layer is approximately 10 to 200 nm thick.
Claim 18
Dependent Claim
14 words
The process as in claim 10, wherein said recess is formed by isotropic etching.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-04 | 2003-04-05 | 2003-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-04 | 2007-04-05 | 2007-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-04 | 2011-04-05 | 2011-10-05 | $7700.00 | Window Closed / Lapsed |