US5674768A
Expired / Lapsed
US
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Method of making flash EEPROM cell having first and second floating gates
Assignee: SK Hynix Inc
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Filing: 1996-03-22
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Granted: 1997-10-07
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Expires: 2016-03-22
Abstract
Abstract This invention relates to a Flash EEPROM (Electrically erasable programmable Read-Only Memory) cell and manufacturing methods thereof, especially which is capable of three different output levels by the variation of effective channel length depending on whether either or all of two floating gates are programmed or erased and the combination of bias, in which two floating gates are formed on a channel region.
Inventors
- 👤 Sang Hwan Chang
- 👤 Sung Oh Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:39
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/0475; H; H10; H10B; H10B41/00; G11C11/00; G11C11/56; G11C11/5621; G11C16/0408; G11C16/0441; G11C16/0458; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; H10P; H10P14/00; H10P14/40; H10P14/416; H10P30/00; H10P30/20; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5612
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
151 words
The method of manufacturing an EEPROM cell, comprising the steps of: forming a first tunnel oxide film on a silicon substrate; forming a first polysilicon pattern to define the width and one side of a first floating gate; forming a dielectric film spacer at a wall of said first polysilicon pattern; forming a second tunnel oxide on the resulting structure after forming said dielectric film spacer; forming a second polysilicon pattern to define the width and one side of a second floating gate at a location parallel to said first polysilicon pattern; sequentially forming a dielectric film and a third polysilicon film; forming a control gate by etching said third polysilicon film using a mask for the control gate in which the other side of the first and second polysilicon patterns are consecutively etched; and forming a source and a drain region on the silicon substrate using an ion implant process.
Claim 2
Independent Claim
151 words
The method of manufacturing an EEPROM cell, comprising the steps of: forming a first tunnel oxide film on a silicon substrate; forming a first polysilicon pattern to define the width and one side of a first floating gate; forming a dielectric film spacer at a wall of said first polysilicon pattern; forming a second tunnel oxide on the resulting structure after forming said dielectric film spacer; forming a second polysilicon pattern to define the width and one side of a second floating gate at a location parallel to said first polysilicon pattern; sequentially forming a dielectric film and a third polysilicon film; forming a control gate by etching said third polysilicon film using a mask for the control gate in which the other side of the first and second polysilicon patterns are consecutively etched; and forming a source and a drain region on the silicon substrate using an ion implant process.
Claim 3
Dependent Claim
22 words
The method of claim 1, wherein one side of said second floating gate overlaps with one side of said first floating gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-06 | 2001-04-07 | 2001-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-06 | 2005-04-07 | 2005-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-06 | 2009-04-07 | 2009-10-07 | $7700.00 | Window Closed / Lapsed |