US5962918A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having simple protective structure and process of fabrication thereof
Assignee: NEC Electronics Corp
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Filing: 1998-10-13
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Granted: 1999-10-05
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Expires: 2018-10-13
Abstract
Abstract A semiconductor integrated circuit device has a protective structure between a semiconductor chip and a ball grid array, and the protective structure has a thin polyimide film bonded to the surface of the semiconductor chip and a thick stress relaxation layer covering conductive strips connected between pads on the surface and the ball grid array; when thermal stress is exerted on the ball grid array, the thick stress relaxation layer allows said ball grid array to move so as to take up the thermal stress.
Inventors
- 👤 Naoto Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:20
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W70/00; H10W70/01; H10W70/05; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/656; H10W72/01; H10W72/019; H10W72/01921; H10W72/01925; H10W72/20; H10W72/251; H10W72/252; H10W72/701; H10W72/921; H10W72/923; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
160 words
A semiconductor device comprising: a semiconductor chip having electric elements connected to conductive pads formed on a major surface thereof, an insulating layer covering said major surface and having holes to which said conductive pads are exposed, conductive strips formed on said insulating layer and having first portions respectively connected to said conductive pads, a stress relaxation layer thicker than said insulating layer, covering said conductive strips and having holes to which second portions of said conductive strips are exposed, solder balls received in said holes in said stress relaxation layer and soldered to said second portions, respectively, and a lifter provided between said second portion of said conductive strips and one of said solder balls for increasing the thickness of said stress relaxation layer, wherein said lifter is formed by a conductive wire bonded at both ends thereof to said second portion at a spacing in such a manner as to project an intermediate portion over said second portion.
Claim 2
Dependent Claim
160 words
A semiconductor device comprising: a semiconductor chip having electric elements connected to conductive pads formed on a major surface thereof, an insulating layer covering said major surface and having holes to which said conductive pads are exposed, conductive strips formed on said insulating layer and having first portions respectively connected to said conductive pads, a stress relaxation layer thicker than said insulating layer, covering said conductive strips and having holes to which second portions of said conductive strips are exposed, solder balls received in said holes in said stress relaxation layer and soldered to said second portions, respectively, and a lifter provided between said second portion of said conductive strips and one of said solder balls for increasing the thickness of said stress relaxation layer, wherein said lifter is formed by a conductive wire bonded at both ends thereof to said second portion at a spacing in such a manner as to project an intermediate portion over said second portion.
Claim 3
Dependent Claim
59 words
The semiconductor device as set forth in claim 1, further comprising a noble metal layer covering an inner surface defining each recess formed in said stress relaxation layer and electrically connected to the second portion of one of said conductive strips, and a solder layer laminated on said noble metal layer and bonded to one of said solder balls.
Claim 4
Dependent Claim
31 words
The semiconductor device as set forth in claim 2, in which said protective insulating layer, said conductive strips and said noble metal layer are formed of polyimide, aluminum and palladium, respectively.
Claim 5
Dependent Claim
133 words
A semiconductor device comprising: a semiconductor chip having electric elements connected to conductive pads formed on a major surface thereof, an insulating layer covering said major surface and having holes to which said conductive pads are exposed, conductive strips formed on said insulating layer and having first portions respectively connected to said conductive pads, a stress relaxation layer thicker than said insulating layer, covering said conductive strips and having holes to which second portions of said conductive strips are exposed, solder balls received in said holes in said stress relaxation layer and soldered to said second portions, respectively, wherein said stress relaxation layer includes a covering layer formed so that said conductive strips are sandwiched between said insulating layer and said covering layer and a spacer layer is laminated on said covering layer.
Claim 6
Dependent Claim
133 words
A semiconductor device comprising: a semiconductor chip having electric elements connected to conductive pads formed on a major surface thereof, an insulating layer covering said major surface and having holes to which said conductive pads are exposed, conductive strips formed on said insulating layer and having first portions respectively connected to said conductive pads, a stress relaxation layer thicker than said insulating layer, covering said conductive strips and having holes to which second portions of said conductive strips are exposed, solder balls received in said holes in said stress relaxation layer and soldered to said second portions, respectively, wherein said stress relaxation layer includes a covering layer formed so that said conductive strips are sandwiched between said insulating layer and said covering layer and a spacer layer is laminated on said covering layer.
Claim 7
Dependent Claim
31 words
The semiconductor device as set forth in claim 4, in which said insulating layer and said covering layer are formed of polyimide, and said spacer layer is formed of epoxy resin.
Claim 8
Dependent Claim
35 words
The semiconductor device as set forth in claim 5, in which said covering layer and said spacer layer are of the order of 10 microns thick and of the order of 100 microns thick, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-04 | 2003-04-05 | 2003-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-04 | 2007-04-05 | 2007-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-04 | 2011-04-05 | 2011-10-05 | $7700.00 | Window Closed / Lapsed |