US5834844A
Expired / Lapsed
US
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Semiconductor device having an element with circuit pattern thereon
Assignee: Shinko Electric Industries Co Ltd
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Filing: 1996-03-22
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Granted: 1998-11-10
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Expires: 2016-03-22
Abstract
Abstract A process for making a chip sized semiconductor device, in which a semiconductor chip is prepared so as to have electrodes on one of surfaces thereof and an electrically insulating passivation film formed on the one surface except for areas where the electrodes exist. An insulation sheet is prepared so as to have first and second surfaces and a metallic film coated on the first surface. The second surface of the insulation sheet is adhered on the one surface of the semiconductor chip. First via-holes are provided in the metallic film at positions corresponding to the electrodes. Second via-holes are provided in the insulation sheet at positions corresponding to the first via-holes so that the electrodes are exposed. The metallic film is electrically connected to the electrodes of the semiconductor chip through the first and second via-holes. A circuit pattern is formed from the metallic film so that the circuit pattern has external terminal connecting portions. An insulation film is adhered on the insulation sheet so that the external terminal connecting portions are exposed. External connecting terminals are electrically connected to the external terminal connecting portions of the circuit pattern.
Inventors
- 👤 Masatoshi Akagawa
- 👤 Mitsutoshi Higashi
- 👤 Hajime Iizuka
- 👤 Takehiko Arai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:05
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/435; H10W20/45; H10W20/47; H10W20/48; H10W42/00; H10W42/20; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W70/00; H10W70/01; H10W70/05; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/656; H10W72/00; H10W72/01; H10W72/012; H10W72/01221; H10W72/01225; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/241; H10W72/242; H10W72/244; H10W72/251; H10W72/252; H10W72/29; H10W72/90; H10W72/921; H10W72/922; H10W72/9223; H10W72/923; H10W72/941; H10W72/9415; H10W72/942
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
146 words
A chip sized semiconductor device comprising: a semiconductor chip having electrodes on a first surface thereof and an electrically insulating passivation film formed on said first surface excluding areas where said electrodes exist; a first insulation film made of a photosensitive resin and formed on said passivation film so that said electrodes are exposed; a circuit pattern formed on said first insulation film so that said circuit pattern has first portions electrically connected to said electrodes of the semiconductor chip, and second portions; a second insulation film formed on said circuit pattern so that said second portions of the circuit pattern are exposed; external connecting terminals electrically connected to said second portions of the circuit pattern; and a metallic protective film formed between first surface of the semiconductor chip and said first insulation film to stop an ultraviolet beam from penetrating therethrough toward said semiconductor chip.
Claim 2
Dependent Claim
146 words
A chip sized semiconductor device comprising: a semiconductor chip having electrodes on a first surface thereof and an electrically insulating passivation film formed on said first surface excluding areas where said electrodes exist; a first insulation film made of a photosensitive resin and formed on said passivation film so that said electrodes are exposed; a circuit pattern formed on said first insulation film so that said circuit pattern has first portions electrically connected to said electrodes of the semiconductor chip, and second portions; a second insulation film formed on said circuit pattern so that said second portions of the circuit pattern are exposed; external connecting terminals electrically connected to said second portions of the circuit pattern; and a metallic protective film formed between first surface of the semiconductor chip and said first insulation film to stop an ultraviolet beam from penetrating therethrough toward said semiconductor chip.
Claim 3
Dependent Claim
22 words
A chip sized semiconductor device as set forth in claim 1, wherein said first insulation film is made of a photo-sensitive polyimide.
Claim 4
Dependent Claim
23 words
A chip sized semiconductor device as set forth in claim 1, wherein said second insulation film is made of a photo-sensitive solder resist.
Claim 5
Dependent Claim
20 words
A chip sized semiconductor device as set forth in claim 1, wherein said external connecting terminals are electrical solder bumps.
Claim 6
Dependent Claim
40 words
A chip sized semiconductor device as set forth in claim 1, further comprising: a protective cover or frame; and a peripheral side surface of the semiconductor chip, wherein said peripheral side surface is protected by said protective cover or frame.
Claim 7
Dependent Claim
47 words
A chip sized semiconductor device as set forth in claim 1, further comprising: a heat spreader; and wherein said semiconductor chip has a second surface and said semiconductor chip is mounted on said heat spreader so that said second surface is in contact with said heat spreader.
Claim 8
Dependent Claim
130 words
A chip sized semiconductor device comprising: a plurality of semiconductor chips arranged side by side, each of said chips having electrodes on a surface thereof and a common electrically insulating passivation film formed on said surface excluding areas where said electrodes exist; a first common insulation film made of a photosensitive resin and formed on said common passivation film so that said electrodes are exposed; circuit patterns formed on said first common insulation film so that said circuit patterns have first portions electrically connected to said electrodes of the respective semiconductor chips, and second portions, a second common insulation film formed on said circuit patterns so that said second portions of each circuit pattern are exposed; and external connecting terminals electrically connected to said second portions of the circuit patterns.
Claim 9
Dependent Claim
130 words
A chip sized semiconductor device comprising: a plurality of semiconductor chips arranged side by side, each of said chips having electrodes on a surface thereof and a common electrically insulating passivation film formed on said surface excluding areas where said electrodes exist; a first common insulation film made of a photosensitive resin and formed on said common passivation film so that said electrodes are exposed; circuit patterns formed on said first common insulation film so that said circuit patterns have first portions electrically connected to said electrodes of the respective semiconductor chips, and second portions, a second common insulation film formed on said circuit patterns so that said second portions of each circuit pattern are exposed; and external connecting terminals electrically connected to said second portions of the circuit patterns.
Claim 10
Dependent Claim
24 words
A chip sized semiconductor device as set forth in claim 7, wherein said second common insulation film is made of a photo-sensitive solder resist.
Claim 11
Dependent Claim
67 words
A chip sized semiconductor device as set forth in claim 7, further comprising: electrically conductive land portions electrically connected to said external connecting terminals; and wherein said second common insulation film has via-holes therein to expose said second portions of the circuit patterns, wherein the electrically conductive land portions are formed on a bottom, an inner wall and a periphery of respective ones of the via holes.
Claim 12
Dependent Claim
36 words
A chip sized semiconductor device as set forth in claim 7, further comprising: a protective cover or frame, and respective side surfaces which form a common peripheral side surface protected by said protective cover or frame.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |