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US5959993A
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Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture
Assignee: Intel Corp
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Filing: 1996-09-13
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Granted: 1999-09-28
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Expires: 2016-09-13
Abstract
Abstract A cell scheduler for a distributed shared memory switch architecture including a controller for scheduling transmissions of cells from output queues of the switch structure pursuant to one of several different scheduling modes. The controller receives a mode selection input, segregates the output queues into groups, assigns priority rankings to the groups, and applies one of scheduling disciplines at each group of output queues as determined by the mode selection input and the priority rankings. The groups of output queues include a group of per-Virtual Channel (VC) queues and at least one group of First In-First Out (FIFO) queues. The scheduling disciplines include a Weighted Fair Queuing (WFQ) scheduling discipline applied by the controller at the group of per-VC queues and a Round Robin (RR) scheduling discipline applied by the controller at the at least one group of FIFO queues. The priority rankings comprising a highest priority ranking which is assigned to the group of per-VC queues.
Inventors
- 👤 Subir Varma
- 👤 Thomas Daniel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:11
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/30; H04L49/10; H04L49/103; H04L49/104; H04L49/105; H04L49/107; H04L49/20; H04L49/3081; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5638; H04L2012/5646; H04L2012/5651; H04L2012/5678; H04L2012/5679; H04L2012/5681
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
159 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the group of output queues comprising a group of per-virtual-channel queues and at least one group of first-in-first-out queues; the plurality of scheduling disciplines comprising a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues and a round-robin scheduling discipline applied by the controller at the at least one group of first-in-first-out queues; the priority rankings comprising a highest priority ranking; and the group of per-virtual-channel queues being assigned the highest priority ranking.
Claim 2
Dependent Claim
159 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the group of output queues comprising a group of per-virtual-channel queues and at least one group of first-in-first-out queues; the plurality of scheduling disciplines comprising a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues and a round-robin scheduling discipline applied by the controller at the at least one group of first-in-first-out queues; the priority rankings comprising a highest priority ranking; and the group of per-virtual-channel queues being assigned the highest priority ranking.
Claim 3
Dependent Claim
114 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the plurality of scheduling disciplines including a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues.
Claim 4
Dependent Claim
114 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the plurality of scheduling disciplines including a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues.
Claim 5
Dependent Claim
27 words
The cell scheduler of claim 2 wherein the priority rankings comprise a highest priority ranking, and the group of per-virtual-channel queues are assigned the highest priority ranking.
Claim 6
Dependent Claim
114 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the plurality of scheduling disciplines including a round-robin scheduling discipline applied by the controller at the group of first-in-first-out queues.
Claim 7
Dependent Claim
114 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the plurality of scheduling disciplines including a round-robin scheduling discipline applied by the controller at the group of first-in-first-out queues.
Claim 8
Dependent Claim
123 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the controller scheduling transmissions of cells from the per-virtual-channel queues such that a virtual channel associated with a particular cell does not share a sub-queue with another virtual channel.
Claim 9
Dependent Claim
123 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the controller scheduling transmissions of cells from the per-virtual-channel queues such that a virtual channel associated with a particular cell does not share a sub-queue with another virtual channel.
Claim 10
Dependent Claim
121 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the controller scheduling transmissions of cells from the per-virtual-channel queues such that a virtual channel associated with a particular cell shares a sub-queue with another virtual channel.
Claim 11
Dependent Claim
121 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the controller scheduling transmissions of cells from the per-virtual-channel queues such that a virtual channel associated with a particular cell shares a sub-queue with another virtual channel.
Claim 12
Dependent Claim
123 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to each groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the controller scheduling transmissions of cells from the first-in-first-out queues such that a virtual channel associated with a particular cell does not share a sub-queue with another virtual channel.
Claim 13
Dependent Claim
123 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to each groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the controller scheduling transmissions of cells from the first-in-first-out queues such that a virtual channel associated with a particular cell does not share a sub-queue with another virtual channel.
Claim 14
Dependent Claim
121 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the controller scheduling transmissions of cells from the first-in-first-out queues such that a virtual channel associated with a particular cell shares a sub-queue with another virtual channel.
Claim 15
Dependent Claim
121 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the controller scheduling transmissions of cells from the first-in-first-out queues such that a virtual channel associated with a particular cell shares a sub-queue with another virtual channel.
Claim 16
Dependent Claim
135 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues and three groups of first-in-first-out queues; and the plurality of scheduling disciplines including a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues and a round-robin scheduling discipline applied by the controller at the groups of first-in-first-out queues.
Claim 17
Dependent Claim
135 words
A cell scheduler for a distributed shared memory switch architecture, the cell scheduler comprising: a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues and three groups of first-in-first-out queues; and the plurality of scheduling disciplines including a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues and a round-robin scheduling discipline applied by the controller at the groups of first-in-first-out queues.
Claim 18
Dependent Claim
27 words
The cell scheduler of claim 9 wherein the priority rankings comprise a highest priority ranking, and the group of per-virtual-channel queues are assigned the highest priority ranking.
Claim 19
Dependent Claim
120 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the plurality of scheduling disciplines including a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues.
Claim 20
Dependent Claim
120 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the plurality of scheduling disciplines including a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues.
Claim 21
Dependent Claim
27 words
The chip set of claim 11 wherein the priority rankings including a highest priority ranking, and the group of per-virtual-channel queues are assigned the highest priority ranking.
Claim 22
Dependent Claim
120 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the plurality of scheduling disciplines including a round-robin scheduling discipline applied by the controller at the group of first-in-first-out queues.
Claim 23
Dependent Claim
120 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the plurality of scheduling disciplines including a round-robin scheduling discipline applied by the controller at the group of first-in-first-out queues.
Claim 24
Dependent Claim
129 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the controller scheduling transmissions of cells from the per-virtual-channel queues such that a virtual channel associated with a particular cell does not share a sub-queue with another virtual channel.
Claim 25
Dependent Claim
129 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the controller scheduling transmissions of cells from the per-virtual-channel queues such that a virtual channel associated with a particular cell does not share a sub-queue with another virtual channel.
Claim 26
Dependent Claim
127 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the controller scheduling transmissions of cells from the per-virtual-channel queues such that a virtual channel associated with a particular cell shares a sub-queue with another virtual channel.
Claim 27
Dependent Claim
127 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues; and the controller scheduling transmissions of cells from the per-virtual-channel queues such that a virtual channel associated with a particular cell shares a sub-queue with another virtual channel.
Claim 28
Dependent Claim
129 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the controller scheduling transmissions of cells from the first-in-first-out queues such that a virtual channel associated with a particular cell does not share a sub-queue with another virtual channel.
Claim 29
Dependent Claim
129 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the controller scheduling transmissions of cells from the first-in-first-out queues such that a virtual channel associated with a particular cell does not share a sub-queue with another virtual channel.
Claim 30
Dependent Claim
127 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the controller scheduling transmissions of cells from the first-in-first-out queues such that a virtual channel associated with a particular cell shares a sub-queue with another virtual channel.
Claim 31
Dependent Claim
127 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of first-in-first-out queues; and the controller scheduling transmissions of cells from the first-in-first-out queues such that a virtual channel associated with a particular cell shares a sub-queue with another virtual channel.
Claim 32
Dependent Claim
141 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues and three groups of first-in-first-out queues; and the plurality of scheduling disciplines including a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues and a round-robin scheduling discipline applied by the controller at the groups of first-in-first-out queues.
Claim 33
Dependent Claim
141 words
A chip set including a cell scheduler for a distributed shared memory switch architecture, the chip set comprising: a plurality of output queues; a controller for scheduling transmissions of cells from the output queues pursuant to one of a plurality of scheduling modes, receiving a mode selection input, segregating the output queues into groups of output queues, assigning priority rankings to the groups, and applying one of a plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings; the groups of output queues including a group of per-virtual-channel queues and three groups of first-in-first-out queues; and the plurality of scheduling disciplines including a weighted-fair-queuing scheduling discipline applied by the controller at the group of per-virtual-channel queues and a round-robin scheduling discipline applied by the controller at the groups of first-in-first-out queues.
Claim 34
Dependent Claim
27 words
The chip set of claim 18 wherein the priority rankings comprise a highest priority ranking, and the group of per-virtual-channel queues are assigned the highest priority ranking.
Claim 35
Independent Claim
107 words
A method of manufacturing a cell scheduler for a distributed shared memory switch architecture, the method comprising the steps of: (a) providing a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, including a weighted-fair-queuing scheduling discipline and a round-robin scheduling discipline; (b) providing the controller with a mode selection input; and (c) employing the controller to segregate the output queues into groups, assign priority rankings to the groups, and apply one of the plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings.
Claim 36
Independent Claim
107 words
A method of manufacturing a cell scheduler for a distributed shared memory switch architecture, the method comprising the steps of: (a) providing a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes, including a weighted-fair-queuing scheduling discipline and a round-robin scheduling discipline; (b) providing the controller with a mode selection input; and (c) employing the controller to segregate the output queues into groups, assign priority rankings to the groups, and apply one of the plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings.
Claim 37
Independent Claim
109 words
A method of manufacturing a cell scheduler for a distributed shared memory switch architecture, the method comprising the steps of: (a) providing a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes; (b) providing the controller with a mode selection input; and (c) employing the controller to segregate the output queues into groups including a group of per-virtual-channel queues and a group of first-in-first-out queues, assign priority rankings to the groups, and apply one of the plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings.
Claim 38
Independent Claim
109 words
A method of manufacturing a cell scheduler for a distributed shared memory switch architecture, the method comprising the steps of: (a) providing a controller for scheduling transmissions of cells from output queues of the switch architecture pursuant to one of a plurality of scheduling modes; (b) providing the controller with a mode selection input; and (c) employing the controller to segregate the output queues into groups including a group of per-virtual-channel queues and a group of first-in-first-out queues, assign priority rankings to the groups, and apply one of the plurality of scheduling disciplines at each of the groups as determined by the mode selection input and the priority rankings.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-27 | 2003-03-29 | 2003-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-27 | 2007-03-29 | 2007-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-27 | 2011-03-29 | 2011-09-28 | $7700.00 | Window Closed / Lapsed |