Message routing

Claim 3

A method as claimed in claim 1 which comprises transmitting said message packet via a plurality of routing switches connected in succession between said source node and said destination node.

Claim 4

A method as claimed in claim 2 in which said message packet is output from said source node with first and second destination node indicators, said method comprising the step of at one of said routing switches deleting said first node indicator so that, on receipt of the packet by a successive routing switch, said second node indicator is used as the header portion.

Claim 5

A method according to claim 3 wherein said first node indicator is deleted from message packets output at all of a selected set of said outputs.

Claim 6

A method as claimed in claim 1 comprising providing a new, randomly generated header portion for said message packet received by said routing switch, and using said new header portion to determine the output of the switch through which the packet is to be routed.

Claim 7

A method according to claim 5 wherein said routing switching comprises a plurality of inputs and said new header portion is provided for message packets received at all of a selected set of said inputs.

Claim 8

A method as claimed in claim 5, in which said packet is routed to another routing switch, the method comprising discarding said randomly generated header portion at said other routing switch identified thereby to reveal said original header portion.

Claim 9

A method as claimed in claim 1 when used to route messages between a first processing device constituting the source node and a second processing device constituting the destination node in which each message packet output by the source node is acknowledged by the destination node when that message packet is received thereby.

Claim 10

A method as claimed in claim 1, wherein said routing switch has a plurality of inputs, the method comprising: supplying a plurality of such message packets serially to at least some of said plurality of inputs; concurrently reading the header portions of said message packets to select an output for each message packet; and transmitting the message portions of said message packets through said routing switch from each input to the respective selected outputs.

Claim 11

A computer network which includes a plurality of nodes having respective identifications, said network comprising: a plurality of computer devices, each including a processor for executing processes, message links for inputting and outputting messages from and to other devices in the network, and packet generating circuitry for generating message packets each with a header portion indicating a destination node identification and a message portion following the header portion; and at least one routing switch for routing message packets between said computer devices, said routing switch including an input for receiving such message packets from a source node, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs, and header reading circuitry for reading the header portion of each message packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion.

Claim 12

A computer network which includes a plurality of nodes having respective identifications, said network comprising: a plurality of computer devices, each including a processor for executing processes, message links for inputting and outputting messages from and to other devices in the network, and packet generating circuitry for generating message packets each with a header portion indicating a destination node identification and a message portion following the header portion; and at least one routing switch for routing message packets between said computer devices, said routing switch including an input for receiving such message packets from a source node, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs, and header reading circuitry for reading the header portion of each message packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion.

Claim 13

A computer network as claimed in claim 10 in which the switch circuitry of the routing switch is operable to effect connection between the input and the selected output in response to reading of the header by the header reading circuitry.

Claim 14

A computer network as claimed in claim 10 in which the switch circuitry is operable to disconnect the input from the selected output on detection of the end of the message packet, thereby to free said output for subsequent message packets.

Claim 15

A computer network as claimed in claim 10 including a plurality of interconnected routing switches so that each message packet uses a succession of such routing switches between the source and destination nodes.

Claim 16

A computer network as claimed in claim 13 wherein said at least one routing switch further includes arbitration circuitry to control the use of an output which has been selected to be connected to more than one input.

Claim 17

A computer network as claimed in claim 13 in which one of said routing switches in said succession further comprises random header generation circuitry operable to generate random addresses to form new header portions for incoming message packets, and another routing switch in said succession further comprises discard circuitry operable to compare the header portion with an identification of the routing switch and to discard the header portion which was previously generated randomly when the random address identifies the routing switch in question.

Claim 18

A computer network as claimed in claim 10 in which said at least one routing switch has a plurality of inputs, each selectively connectable to any of said plurality of outputs.

Claim 19

A computer network according to claim 10 in which the packet generating circuitry of each computer device is arranged to produce serial bit packets having a predetermined bit length, said at least one routing switch having a storage portion, for header portions of the message packets, coupled to the header reading circuitry and having a bit capacity less than the bit length of the serial bit packets generated by the packet generating circuitry.

Claim 20

A computer network as claimed in claim 10 in which each message packet is generated with first and second destination node indicators and in which said at least one routing switch further comprises deletion circuitry for deleting the first node indicator of the message packet received thereby so that on receipt of the message packet by a successive routing switch, the second node indicator is used as the header portion.

Claim 21

A computer network as claimed in claim 10 in which said at least one routing switch further comprises random header generation circuitry operable to generate random addresses to form new header portions for incoming message packets.

Claim 22

A routing switch for routing messages between computer devices in a network which includes a plurality of nodes having respective identifications, each computer device including packet generating circuitry for generating message packets with a header portion indicating a destination node identification and a message portion following the header portion, said routing switch including an input for receiving message packets from a source node, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion.

Claim 23

A routing switch for routing messages between computer devices in a network which includes a plurality of nodes having respective identifications, each computer device including packet generating circuitry for generating message packets with a header portion indicating a destination node identification and a message portion following the header portion, said routing switch including an input for receiving message packets from a source node, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion.

Claim 24

A routing switch as claimed in claim 20 which has a plurality of inputs, each selectively connectable to any of said plurality of outputs.

Claim 25

A routing switch as claimed in claim 21, in which the header reading circuitry comprises a plurality of header reading circuits, said header reading circuits being operable to read the header portions of message packets received concurrently by said switch.

Claim 26

A routing switch as claimed in claim 22 in which said plurality of header reading circuits comprises a header reading circuit associated respectively with each of said inputs of the routing switch.

Claim 27

A routing switch as claimed in claim 20 in which the switch circuitry is operable to effect connection between the input and the selected output in response to reading of the header by the header reading circuitry.

Claim 28

A routing switch as claimed in claim 20, in which the switch circuitry is operable to disconnect the input from the selected output on detection of the end of the message packet, thereby to free said output for subsequent message packets.

Claim 29

A routing switch as claimed in claim 20 in which each message packet is generated with first and second destination node indicators and in which the routing switch further comprises header deletion circuitry for deleting the first node indicator of the message packet received thereby so that on receipt of the message packet by a successive routing switch connected thereto, the second node indicator is used as the header portion.

Claim 30

A routing switch as claimed in claim 20 which further comprises random header generation circuitry operable to generate random addresses to form new header portions for incoming message packets.

Claim 31

A routing switch as claimed in claim 20 which has arbitration circuitry to control the use of an output which has been selected to be connected to more than one input.

Claim 34

A method according to claim 29 wherein said first node indicator is deleted from message packets output at all of a selected set of said outputs.

Claim 35

A computer network which includes a plurality of nodes having respective identifications, said network comprising: a plurality of computer devices, each including a processor for executing processes, message links for inputting and outputting messages from and to other devices in the network, and packet generating circuitry for generating message packets each with a header portion indicating a destination node identification and a message portion following the header portion; at least one routing switch for routing message packets between said computer devices, said routing switch including an input for receiving such message packets from a source node, a plurality of outputs each destination a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs, and header reading circuitry for reading the header portion of each message packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion; each message packet being generated with first and second destination node indicators; and said at least one routing switch further comprising deletion circuitry for deleting the first node indicator of the message packet received thereby so that on receipt of the message packet by a successive routing switch, the second node indicator is used as the header portion.

Claim 36

A computer network which includes a plurality of nodes having respective identifications, said network comprising: a plurality of computer devices, each including a processor for executing processes, message links for inputting and outputting messages from and to other devices in the network, and packet generating circuitry for generating message packets each with a header portion indicating a destination node identification and a message portion following the header portion; at least one routing switch for routing message packets between said computer devices, said routing switch including an input for receiving such message packets from a source node, a plurality of outputs each destination a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs, and header reading circuitry for reading the header portion of each message packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion; each message packet being generated with first and second destination node indicators; and said at least one routing switch further comprising deletion circuitry for deleting the first node indicator of the message packet received thereby so that on receipt of the message packet by a successive routing switch, the second node indicator is used as the header portion.

Claim 37

A routing switch for routing messages between computer devices in a network which includes a plurality of nodes having respective identification, each computer device including packet generating circuitry for generating message packets with a header portion indicating a destination node identification and a message portion following the header portion, said routing switch including an input for receiving message packets from a source node, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion; each message packet being generated with a header portion comprising first and second destination node indicators; and said routing switch further comprising header deletion circuitry for deleting the first node indicator of the message packet received thereby so that on receipt of the message packet by a successive routing switch connected thereto, the second node indicator is used as the header portion.

Claim 38

A routing switch for routing messages between computer devices in a network which includes a plurality of nodes having respective identification, each computer device including packet generating circuitry for generating message packets with a header portion indicating a destination node identification and a message portion following the header portion, said routing switch including an input for receiving message packets from a source node, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion; each message packet being generated with a header portion comprising first and second destination node indicators; and said routing switch further comprising header deletion circuitry for deleting the first node indicator of the message packet received thereby so that on receipt of the message packet by a successive routing switch connected thereto, the second node indicator is used as the header portion.

Claim 39

A computer network which includes a plurality of nodes having respective identifications, said network comprising: a plurality of computer devices, each including a processor for executing processes, message links for inputting and outputting messages from and to other devices in the network, and packet generating circuitry for generating message packets each with a header portion indicating a destination node identification and a message portion following the header portion; a plurality of interconnected routing switches, each said routing switch including an input for receiving such message packets from a source node, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs, and header reading circuitry for reading the header portion of each message packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect said input to one of said outputs having a node identification range including the node identification of said header portion; each message packet using a succession of said routing switches between the source and destination nodes; and one of said routing switches in said succession further comprising random header generation circuitry operable to generate random addresses to form new header portions for incoming message packets, and another routing switch in said succession further comprises discard circuitry operable to compare the header portion with identification of the routing switch and to discard the header portion which was previously generated randomly when the random address identifies the routing switch in question.

Claim 40

A computer network which includes a plurality of nodes having respective identifications, said network comprising: a plurality of computer devices, each including a processor for executing processes, message links for inputting and outputting messages from and to other devices in the network, and packet generating circuitry for generating message packets each with a header portion indicating a destination node identification and a message portion following the header portion; a plurality of interconnected routing switches, each said routing switch including an input for receiving such message packets from a source node, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs, and header reading circuitry for reading the header portion of each message packet received at the input prior to receiving all of the message packet, said header reading circuitry being coupled to said switch circuitry to connect said input to one of said outputs having a node identification range including the node identification of said header portion; each message packet using a succession of said routing switches between the source and destination nodes; and one of said routing switches in said succession further comprising random header generation circuitry operable to generate random addresses to form new header portions for incoming message packets, and another routing switch in said succession further comprises discard circuitry operable to compare the header portion with identification of the routing switch and to discard the header portion which was previously generated randomly when the random address identifies the routing switch in question.