Self-routing switch element for an asynchronous time switch

Claim 2

A self-routing switching element for use in an asynchronous time switch, comprising: a plurality of selectors each having an input for incoming tagged packet signals; a plurality of arbiters each having an output for a transmitted packet signal; and a signal path connection between each of said plurality of selectors and each of said plurality of arbiters; wherein each of said plurality of selectors is operable to examine the tag of an incoming tagged packet signal and route said incoming tagged packet signal to one of said plurality of arbiters identified by said examined tag, and wherein each of said plurality of arbiters is operable to select a first packet signal received from any of said plurality of selectors and transmit said first packet signal to its output, and to act on other ones of said plurality of selectors to prevent subsequent incoming tagged packet signals from being transmitted until said first packet signal is transmitted.

Claim 3

The invention set forth in claim 1 wherein each of said plurality of selectors is operable to generate an active signal in response to the presence of a valid incoming tagged packet signal at its input; said one of said plurality of arbiters acting on those of said plurality of selectors at which an active signal is detected to prevent subsequent incoming tagged packet signals from being transmitted until said first packet signal is transmitted.

Claim 4

The invention set forth in claim 2 wherein each of said plurality of arbiters includes priority selection means for selecting a first active signal from one of said plurality of selectors and transmitting the packet signal from said one of said plurality of selectors.

Claim 5

The invention set forth in claim 2 wherein said signal path connection includes a data signal path for transmission of packet signals and an active signal path for transmission of an active signal detected by said one of said plurality of arbiters.

Claim 6

The invention set forth in claim 1 wherein the one of said plurality of arbiters receiving said first packet signal generates a busy signal which is passed back to said plurality of selectors to inhibit transmission of subsequent incoming tagged packet signals.

Claim 7

The invention set forth in claim 5 wherein said signal path connection includes a busy signal path for transmission of said busy signal from said one of said plurality of arbiters to said plurality of selectors.

Claim 8

An asynchronous time switch comprising: a plurality of input port controllers; an input buffer containing a queue of incoming packet signals from which each of said plurality of input port controllers is fed; a plurality of output port controllers; an output buffer fed by each of said plurality of output port controllers; and a switch fabric interconnecting said plurality of input port controllers and said plurality of output port controllers, wherein said switch fabric comprises a plurality of switching elements providing a signal path connection between each of said plurality of input port controllers and each of said plurality of output port controllers and wherein said switch fabric includes. a plurality of selectors each having an input from one of said input port controllers for receiving incoming packet signals having tags; a plurality of arbiters each having an output to one of said output port controllers for transmitting packet signals having tags; a signal path connection between each of said plurality of selectors and each of said plurality of arbiters; each of said plurality of selectors operable to examine tags to route said incoming tagged packet signals to said plurality of arbiters as transmitted tagged packet signals.

Claim 9

An asynchronous time switch comprising: a plurality of input port controllers; an input buffer containing a queue of incoming packet signals from which each of said plurality of input port controllers is fed; a plurality of output port controllers; an output buffer fed by each of said plurality of output port controllers; and a switch fabric interconnecting said plurality of input port controllers and said plurality of output port controllers, wherein said switch fabric comprises a plurality of switching elements providing a signal path connection between each of said plurality of input port controllers and each of said plurality of output port controllers and wherein said switch fabric includes. a plurality of selectors each having an input from one of said input port controllers for receiving incoming packet signals having tags; a plurality of arbiters each having an output to one of said output port controllers for transmitting packet signals having tags; a signal path connection between each of said plurality of selectors and each of said plurality of arbiters; each of said plurality of selectors operable to examine tags to route said incoming tagged packet signals to said plurality of arbiters as transmitted tagged packet signals.

Claim 10

The invention set forth in claim 7 wherein a plurality of signal paths is provided between each of said plurality of input port controllers and each of said plurality of output port controllers.

Claim 11

An asynchronous time switch comprising: a plurality of inputs; a plurality of outputs; a plurality of switching elements operable to connect said plurality of inputs and said plurality of outputs so as to define a plurality of signal paths between each of said plurality of inputs and each of said plurality of outputs; input control means operable to transmit copies of a packet signal substantially simultaneously along all of said plurality of signal paths between one of said plurality of inputs and one of said plurality of outputs; and output control means operable to detect a single copy of said packet signal received at one of said plurality of outputs from one of said plurality of signal paths and to prevent subsequent copies of said packet signal from being transmitted along others of said plurality of signal paths.

Claim 12

An asynchronous time switch comprising: a plurality of inputs; a plurality of outputs; a plurality of switching elements operable to connect said plurality of inputs and said plurality of outputs so as to define a plurality of signal paths between each of said plurality of inputs and each of said plurality of outputs; input control means operable to transmit copies of a packet signal substantially simultaneously along all of said plurality of signal paths between one of said plurality of inputs and one of said plurality of outputs; and output control means operable to detect a single copy of said packet signal received at one of said plurality of outputs from one of said plurality of signal paths and to prevent subsequent copies of said packet signal from being transmitted along others of said plurality of signal paths.

Claim 13

The invention set forth in claim 9 wherein at least some of said plurality of switching elements are self-routing switching elements.

Claim 14

An asynchronous time switch operable to transmit tagged packet signals carrying voice class information and tagged packet signals carrying data class information comprising: a plurality of inputs; a plurality of outputs; a plurality of switching elements having a plurality of signal paths between each of said plurality of inputs and each of said plurality of outputs; input control means operable to distinguish whether an incoming one of said tagged packet signals to be transmitted is carrying voice class information or data class information; wherein said input control means is further operable to transmit said tagged packet signals carrying data class information over one or more signal paths only when all said tagged packet signals carrying voice class information have been transmitted.

Claim 15

An asynchronous time switch operable to transmit tagged packet signals carrying voice class information and tagged packet signals carrying data class information comprising: a plurality of inputs; a plurality of outputs; a plurality of switching elements having a plurality of signal paths between each of said plurality of inputs and each of said plurality of outputs; input control means operable to distinguish whether an incoming one of said tagged packet signals to be transmitted is carrying voice class information or data class information; wherein said input control means is further operable to transmit said tagged packet signals carrying data class information over one or more signal paths only when all said tagged packet signals carrying voice class information have been transmitted.

Claim 16

The invention set forth in claim 11 wherein said input control means is further operable to modify the tag of said incoming one of said tagged packet signals to be transmitted whereby said modified tag identifies whether said incoming one of said tagged packet signals is carrying voice class information or data class information.

Claim 17

The invention set forth in claim 11 having output control means operable to detect said tagged packet signals carrying voice class information and to prevent transmission of all said tagged packet signals carrying data class information when one of said tagged packet signals carrying voice class information has been detected until said detected tagged packet signal carrying voice class information has been transmitted.