Patent US5959488A successfully refreshed from Google Patents.
US5959488A
Expired / Lapsed
US
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Dual-node capacitor coupled MOSFET for improving ESD performance
Assignee: Winbond Electronics Corp
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Filing: 1998-01-24
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Granted: 1999-09-28
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Expires: 2018-01-24
Abstract
Abstract A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time, the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.
Inventors
- 👤 Shi-Tron Lin
- 👤 Shyh-Chyi Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:33
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
70 words
An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising: a MOSFET device having a source, a drain, a gate and a bulk; a capacitor connected between the gate of said MOSFET and a pad terminal; a first resistor connected between the gate and the bulk of said MOSFET; and a second resistor connected between the bulk and a power bus.
Claim 2
Dependent Claim
70 words
An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising: a MOSFET device having a source, a drain, a gate and a bulk; a capacitor connected between the gate of said MOSFET and a pad terminal; a first resistor connected between the gate and the bulk of said MOSFET; and a second resistor connected between the bulk and a power bus.
Claim 3
Dependent Claim
14 words
The circuit of claim 1, wherein said source is connected to said power bus.
Claim 4
Dependent Claim
11 words
The circuit of claim 1, wherein said MOSFET is a PMOSFET.
Claim 5
Dependent Claim
11 words
The circuit of claim 3, wherein said power bus is VDD.
Claim 6
Dependent Claim
25 words
The circuit of claim 1, further comprising multiple MOSFET devices connected in parallel, wherein all gates of said multiple MOSFET devices are electrically connected together.
Claim 7
Dependent Claim
19 words
The circuit of claim 5, wherein at least two drains of said multiple MOSFET devices are electrically connected together.
Claim 8
Dependent Claim
17 words
The circuit of claim 5, wherein at least two MOSFET devices share a common drain diffusion region.
Claim 9
Dependent Claim
19 words
The circuit of claim 5, wherein at least two sources of said multiple MOSFET devices are electrically connected together.
Claim 10
Dependent Claim
17 words
The circuit of claim 5, wherein at least two MOSFET devices share a common source diffusion region.
Claim 11
Dependent Claim
14 words
The circuit of claim 5, wherein said multiple MOSFET devices form a multi-finger structure.
Claim 12
Dependent Claim
16 words
The circuit of claim 1, wherein said drain is connected between said pad and a buffer.
Claim 13
Dependent Claim
41 words
The circuit of claim 11, wherein said bulk is a p-well, said p-well having a voltage potential of approximately 0.7 V, and said gate has a voltage potential approximately in the range of 1.0 to 2.0 V during as ESD event.
Claim 14
Dependent Claim
11 words
The circuit of claim 1, wherein said MOSFET is an NMOSFET.
Claim 15
Dependent Claim
12 words
The circuit of claim 13, wherein said power bus is a GND.
Claim 16
Dependent Claim
18 words
The circuit of claim 1, further comprising a third resistor connected between said pad terminal and a buffer.
Claim 17
Dependent Claim
18 words
The circuit of claim 15, further comprising a second MOSFET coupled between said buffer and said power bus.
Claim 18
Dependent Claim
72 words
An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising: a MOSFET device having a source, a drain, a gate and a bulk; a capacitor connected between the gate of said MOSFET and a first power bus; a first resistor connected between the gate and the bulk of said MOSFET; and a second resistor connected between the bulk and a second power bus.
Claim 19
Dependent Claim
72 words
An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising: a MOSFET device having a source, a drain, a gate and a bulk; a capacitor connected between the gate of said MOSFET and a first power bus; a first resistor connected between the gate and the bulk of said MOSFET; and a second resistor connected between the bulk and a second power bus.
Claim 20
Dependent Claim
23 words
The circuit of claim 17, wherein said first power bus is a VDD bus and said second power bus is a VSS bus.
Claim 21
Dependent Claim
21 words
The circuit of claim 17, wherein said first power bus is a VDD bus and said second power bus is GND.
Claim 22
Dependent Claim
31 words
The circuit of claim 17, wherein said drain of said MOSFET is connected to said first power bus and said source of said MOSFET is connected to said second power bus.
Claim 23
Dependent Claim
16 words
The circuit of claim 17, wherein said second resistor is in series with said first resistor.
Claim 24
Dependent Claim
48 words
An ESD protection structure, comprising: a MOSFET device comprising a source, a drain, a gate and a body; a capacitor coupled between said gate and said drain; a first resistor coupled between said gate and said body; and a second resistor coupled between said body and said source.
Claim 25
Dependent Claim
48 words
An ESD protection structure, comprising: a MOSFET device comprising a source, a drain, a gate and a body; a capacitor coupled between said gate and said drain; a first resistor coupled between said gate and said body; and a second resistor coupled between said body and said source.
Claim 26
Dependent Claim
14 words
The circuit of claim 22, wherein said source is connected to a power bus.
Claim 27
Dependent Claim
12 words
The circuit of claim 23, wherein said power bus is a GND.
Claim 28
Dependent Claim
11 words
The circuit of claim 22, wherein said MOSFET is a PMOSFET.
Claim 29
Dependent Claim
25 words
The circuit of claim 22, further comprising multiple MOSFET devices connected in parallel, wherein all gates of said multiple MOSFET devices are electrically connected together.
Claim 30
Dependent Claim
19 words
The circuit of claim 26, wherein at least two drains of said multiple MOSFET devices are electrically connected together.
Claim 31
Dependent Claim
17 words
The circuit of claim 26, wherein at least two MOSFET devices share a common drain diffusion region.
Claim 32
Dependent Claim
19 words
The circuit of claim 26, wherein at least two sources of said multiple MOSFET devices are electrically connected together.
Claim 33
Dependent Claim
17 words
The circuit of claim 26, wherein at least two MOSFET devices share a common source diffusion region.
Claim 34
Dependent Claim
14 words
The circuit of claim 26, wherein said multiple MOSFET devices form a multi-finger structure.
Claim 35
Dependent Claim
16 words
The circuit of claim 22, wherein said drain is connected between a pad and a buffer.
Claim 36
Dependent Claim
11 words
The circuit of claim 22, wherein said MOSFET is an NMOSFET.
Claim 37
Dependent Claim
17 words
The circuit of claim 22, further comprising a third resistor connected between said drain and a buffer.
References Cited (Backward Citations)
US4423431A
Cited
US5528188A
Cited
US5631793A
Cited
US5721656A
Cited
US5818086A
Cited
US5686751A
Cited
US5852541A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-27 | 2003-03-29 | 2003-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-27 | 2007-03-29 | 2007-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-27 | 2011-03-29 | 2011-09-28 | $7700.00 | Window Closed / Lapsed |