US5852541A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Early trigger of ESD protection device by an oscillation circuit
Assignee: Winbond Electronics Corp
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Filing: 1997-10-22
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Granted: 1998-12-22
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Expires: 2017-10-22
Abstract
Abstract A transient oscillating circuit is provided to generate a series of current pulses for triggering turn-on of an ESD protection device. As VDD-to-VSS voltage increases rapidly in the initial ESD event, the series of current pulses injects minority carriers into the pwell of an NMOS transistor via an adjacent n+/pwell diode. These minority carriers flow toward the drain-substrate junction of the NMOS transistor such that the NMOS transistor is triggered at a trigger voltage lower than that provided by the prior arts. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.
Inventors
- 👤 Shi-Tron Lin
- 👤 Hao-Luen Tien
- 👤 Shyh-Chyi Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:09
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H02; H02H; H02H9/00; H02H9/04; H02H9/045; H02H9/046
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
118 words
An electrostatic discharge (ESD) protection structure for an integrated circuit constructed on a substrate of a first type, comprising: an ESD protection means constructed on the substrate; an oscillation means having an output terminal for generating an oscillation signal of a first voltage polarity during an ESD event; a pulse-generator means, responsive to the oscillation signal, for generating electric pulses including at least pulses of a second voltage polarity opposite to said first voltage polarity during the ESD event; a minority-carrier injection means, having an input terminal adapted to receive said electric pulses, for injecting minority carriers into the substrate which triggers turn-on of the ESD protection means to conduct a large current due to the ESD event.
Claim 2
Dependent Claim
118 words
An electrostatic discharge (ESD) protection structure for an integrated circuit constructed on a substrate of a first type, comprising: an ESD protection means constructed on the substrate; an oscillation means having an output terminal for generating an oscillation signal of a first voltage polarity during an ESD event; a pulse-generator means, responsive to the oscillation signal, for generating electric pulses including at least pulses of a second voltage polarity opposite to said first voltage polarity during the ESD event; a minority-carrier injection means, having an input terminal adapted to receive said electric pulses, for injecting minority carriers into the substrate which triggers turn-on of the ESD protection means to conduct a large current due to the ESD event.
Claim 3
Dependent Claim
28 words
The structure of claim 1, wherein the oscillation means comprises: N inverters serially connected to each other to form a ring oscillator, wherein N is an odd number.
Claim 4
Dependent Claim
63 words
The structure of claim 2, wherein the oscillation means further comprises a buffer which has an input and an output, the input of the buffer couples to an output terminal of one of said N inverters, the output of the buffer defines the output terminal of the oscillation means, said buffer boosts the driving strength of the oscillation signal during the ESD event.
Claim 5
Dependent Claim
84 words
The structure of claim 1, said electric pulses further including pulses of the first voltage polarity, wherein the pulse-generator means comprises: a capacitive coupling means having a first terminal defining an input terminal of the pulse-generator means, and having a second terminal defining an output terminal of the pulse-generator means; a voltage clamping means coupled between said output terminal of the pulse-generator means and said substrate, for limiting the electric pulses at the output terminal to a clamping voltage of said first voltage polarity.
Claim 6
Dependent Claim
27 words
The structure of claim 1, further comprising a delay-switch means operative to turn on the oscillation means for at least a time period during the ESD event.
Claim 7
Dependent Claim
37 words
The structure of claim 5, wherein the oscillation means comprises: N inverters serially connected to each other, N is an odd number, the last of the N inverters generates the oscillation signal at an output terminal thereof.
Claim 8
Dependent Claim
86 words
The structure of claim 6, wherein the delay-switch means comprises: a switch means having an input node, an output node and a control node, wherein said input node connects to the output terminal of the last of N inverters, said output node connects to an input terminal of the first of N inverters; a control signal generator for generating a control signal to said control node of the switch means to turn on the switch means for at least a time period during the ESD event.
Claim 9
Dependent Claim
21 words
The structure of claim 7, wherein said control signal keeps said switch means off during normal operation of the integrated circuit.
Claim 10
Dependent Claim
21 words
The structure of claim 7, wherein said control signal keeps said switch means off during power-on operation of the integrated circuit.
Claim 11
Dependent Claim
29 words
The structure of claim 7, wherein said control signal generator includes an RC circuit having a resistor and a capacitor with one common joint terminal generating the control signal.
Claim 12
Dependent Claim
24 words
The structure of claim 7, wherein said switch means is a MOSFET transistor, and said control node is a gate of the MOSFET transistor.
Claim 13
Dependent Claim
115 words
The structure of claim 1, wherein the oscillation means comprises: a NAND gate having a first input terminal, a second input terminal and an output terminal; N inverters serially connected to each other, N being an even number, wherein an.output terminal of the last of the N inverters connects to the first terminal of the NAND gate, an input terminal of the first of the N inverters connects to the output terminal of the NAND gate; a control signal generator for generating a control signal to said second input terminal of the NAND gate, the control signal selectively enables the switching of said NAND gate, for at least a time period during the ESD event.
Claim 14
Dependent Claim
25 words
The structure of claim 12, wherein the control signal selectively keeps said NAND gate in a non-switching state during normal operation of the integrated circuit.
Claim 15
Dependent Claim
25 words
The structure of claim 12, wherein the control signal selectively keeps said NAND gate in a non-switching state during power-on operation of the integrated circuit.
Claim 16
Dependent Claim
29 words
The structure of claim 12, wherein said control signal generator includes: an RC circuit having a resistor and a capacitor with one common joint terminal generating the control signal.
Claim 17
Dependent Claim
13 words
The structure of claim 4, wherein said voltage clamping means is a diode.
Claim 18
Dependent Claim
40 words
The structure of claim 4, wherein said voltage clamping means is a diffusion diode formed by a diffusion region of the first type in a well region of a second type, wherein said well region electrically connects to the substrate.
Claim 19
Dependent Claim
14 words
The structure of claim 4, wherein said voltage clamping means is a diode-configured MOSFET.
Claim 20
Dependent Claim
62 words
The structure of claim 4, wherein said voltage clamping means is a diode-configured MOSFET inside a well of a second type, wherein a gate and a drain terminal of the MOSFET is electrically connected to the substrate, while a source terminal of the MOSFET and the well of the second type is electrically connected to said output terminal of the pulse-generator means.
Claim 21
Dependent Claim
14 words
The structure of claim 1, wherein the ESD protection means is a bipolar transistor.
Claim 22
Dependent Claim
14 words
The structure of claim 1, wherein the ESD protection means is a MOSFET transistor.
Claim 23
Dependent Claim
13 words
The structure of claim 1, wherein the ESD protection means is a diode.
Claim 24
Dependent Claim
26 words
The structure of claim 1, wherein the minority-carrier injection means is a diffusion diode formed by a diffusion region of a second type in the substrate.
Claim 25
Dependent Claim
36 words
The structure of claim 23, wherein said diffusion region of the second type is adjacent to a high-electric-field diffusion junction of the ESD protection means, said high-electric-field diffusion junction is reverse biased during the ESD event.
Claim 26
Dependent Claim
37 words
The structure of claim 23, wherein the minority carriers are injected into the substrate via the diffusion diode under forward-bias state which is caused by the electric pulse of the second voltage polarity during the ESD event.
Claim 27
Dependent Claim
39 words
The structure of claim 25, wherein the minority carriers enhance majority or minority carriers generation caused by impact ionization at the high-electric-field diffusion junction of the ESD protection means, the high-electric-field diffusion junction is reversed-biased during the ESD event.
Claim 28
Dependent Claim
24 words
The structure of claim 1, wherein, during the ESD event, an ESD zapping voltage is applied between a VDD pin and a VSS pin.
Claim 29
Dependent Claim
24 words
The structure of claim 1, wherein, during the ESD event, an ESD zapping voltage is applied between an IC pin and a power-bus pin.
Claim 30
Dependent Claim
25 words
The structure of claim 1, wherein, during the ESD event, an ESD zapping voltage is applied between an IC pin and a VSS bus pin.
Claim 31
Dependent Claim
31 words
The structure of claim 29, wherein a VDD power line is connected to said IC pin via a pull up diode, said oscillation means is powered by the VDD and VSS.
Claim 32
Dependent Claim
31 words
The structure of claim 29, wherein a VDD power line is connected to said IC pin via a pull up PMOSFET, said oscillation means is powered by the VDD and VSS.
Claim 33
Independent Claim
110 words
A method for triggering an electrostatic discharge (ESD) protection circuit for an integrated circuit constructed on a substrate of a first type, the ESD protection circuit including an ESD protection means constructed on the substrate, comprising the following steps: generating an oscillation signal of a first voltage polarity during an ESD event; generating, responsive to the oscillation signal, electric pulses including at least pulses of a second voltage polarity opposite to said first voltage polarity; applying said electric pulses to a minority-carrier injection means for injecting minority carriers into the substrate which triggers the turn-on of the ESD protection means to conduct a large current due to the ESD event.
Claim 34
Independent Claim
110 words
A method for triggering an electrostatic discharge (ESD) protection circuit for an integrated circuit constructed on a substrate of a first type, the ESD protection circuit including an ESD protection means constructed on the substrate, comprising the following steps: generating an oscillation signal of a first voltage polarity during an ESD event; generating, responsive to the oscillation signal, electric pulses including at least pulses of a second voltage polarity opposite to said first voltage polarity; applying said electric pulses to a minority-carrier injection means for injecting minority carriers into the substrate which triggers the turn-on of the ESD protection means to conduct a large current due to the ESD event.
Claim 35
Dependent Claim
26 words
The method of claim 32, wherein the minority-carrier injection means is a diffusion diode formed by a diffusion region of a second type in the substrate.
Claim 36
Dependent Claim
36 words
The method of claim 33, wherein said diffusion region of the second type is adjacent to a high-electric-field diffusion junction of the ESD protection means, said high-electric-field diffusion junction is reverse biased during the ESD event.
Claim 37
Dependent Claim
37 words
The method of claim 33, wherein the minority carriers are injected into the substrate via the diffusion diode under forward-bias state which is caused by the electric pulse of the second voltage polarity during the ESD event.
Claim 38
Dependent Claim
39 words
The method of claim 35, wherein the minority carriers enhance majority or minority carriers generation caused by impact ionization at the high-electric-field diffusion junction of the ESD protection means, the high-electric-field diffusion junction is reversed-biased during the ESD event.
References Cited (Backward Citations)
US4503448A
Cited
US4958121A
Cited
US5290724A
Cited
US5272371A
Cited
US5313111A
Cited
US5218222A
Cited
US5508224A
Cited
US5545910A
Cited
US5708549A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-21 | 2002-06-22 | 2002-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-21 | 2006-06-22 | 2006-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-21 | 2010-06-22 | 2010-12-22 | $7700.00 | Window Closed / Lapsed |