Patent FR944890A successfully refreshed from Google Patents.
Patent US5944813A successfully refreshed from Google Patents.
US5944813A
Expired / Lapsed
US
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FPGA input output buffer with registered tristate enable
Assignee: Xilinx Inc
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Filing: 1997-04-08
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Granted: 1999-08-31
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Expires: 2017-04-08
Abstract
Abstract In accordance with the present invention, an FPGA input/output buffer including at least two registers is provided. A first register provides the FPGA output through a tristate buffer to the pad or pin. A second register controls the state of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the second register and for loading data into the first register.
Inventors
- 👤 Stephen M. Trimberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814; G06F15/7867; H03K19/1733; H03K19/1737; H03K19/17724; H03K19/17732
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
56 words
An input output buffer for an FPGA, comprising: a pad; a tristate buffer optionally driving said pad and having a tristate control terminal; a first flip-flop providing an output signal through said tristate buffer to said pad; and a second flip-flop providing a signal to said tristate control terminal for controlling impedance of said tristate buffer.
Claim 2
Dependent Claim
56 words
An input output buffer for an FPGA, comprising: a pad; a tristate buffer optionally driving said pad and having a tristate control terminal; a first flip-flop providing an output signal through said tristate buffer to said pad; and a second flip-flop providing a signal to said tristate control terminal for controlling impedance of said tristate buffer.
Claim 3
Dependent Claim
15 words
The input output buffer of claim 1, wherein said first and second flip-flops are addressable.
Claim 4
Dependent Claim
16 words
The input output buffer of claim 1, wherein said first and second flip-flops are separately addressable.
Claim 5
Dependent Claim
25 words
The input output buffer of claim 1, further comprising: a third flip-flop driven by said pad and optionally providing an input signal to said FPGA.
Claim 6
Dependent Claim
16 words
The input output buffer of claim 4, wherein said first, second, and third flip-flops are addressable.
Claim 7
Dependent Claim
17 words
The input output buffer of claim 4, wherein said first, second, and third flip-flops are separately addressable.
References Cited (Backward Citations)
US4124899A
Cited
US4124899B1
Cited
US4870302A
Cited
US4706216A
Cited
US4758745A
Cited
US5600265A
Cited
US4758745B1
Cited
US4906862A
Cited
US4847612A
Cited
US5490074A
Cited
US5363494A
Cited
US5428800A
Cited
US5444393A
Cited
US5636348A
Cited
US5331571A
Cited
US5361373A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-30 | 2003-03-01 | 2003-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-30 | 2007-03-01 | 2007-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-30 | 2011-03-01 | 2011-08-31 | $7700.00 | Window Closed / Lapsed |