Constant delay interconnect for coupling configurable logic blocks

Claim 2

A programmable integrated circuit comprising: (a) a plurality of programmably configurable logic blocks for carrying out program-defined logic functions, each of said configurable logic blocks having longline input means for inputting signals to the respective configurable logic block, and general output means for outputting signals from the respective logic block; and (b) a programmably configurable interconnect network for providing program-defined routing of signals between the plurality of programmably configurable logic blocks, wherein said configurable interconnect network includes: (b.1) a first group of at least four longlines, said first group of longlines extending by a first subset of at least four of the configurable logic blocks; and (b.2) a first symmetrical distribution of programmable interconnect means provided along the first group of longlines for providing program-defined coupling between respective combinations of more than one but not all of the first group of longlines and corresponding combinations of more than one but not all of the first subset of configurable logic blocks, the first symmetrical distribution of the programmable interconnect means being such that a substantially same signal propagation delay develops for each longline in said first group when intercoupling a corresponding one or more of the first subset of configurable logic blocks.

Claim 3

A programmable integrated circuit according to claim 1 wherein: said plurality of programmably configurable logic blocks is in the form of an array, the array having respective first and second planar dimensions extending horizontally and vertically; said first group of longlines extend substantially across the first planar dimension of the array for providing global interconnect in the horizontal direction; a first of said configurable logic blocks in the first subgroup is positioned near one edge of the array; a second of said configurable logic blocks in the first subgroup is positioned near an opposed second edge of the array; a third of said configurable logic blocks in the first subgroup is positioned approximately midway between the opposed first and second edges of the array; and said first symmetrical distribution of programmable interconnect means is such that a substantially same signal propagation delay develops for intercoupling the first and second by way of the first group of longlines and for intercoupling the third configurable logic block with either of the first and second configurable logic blocks.

Claim 4

A programmable integrated circuit according to claim 1 wherein: the longline input means of a first of said configurable logic blocks in the first subgroup connects to a first line in said first group of longlines; the longline input means of a second of said configurable logic blocks in the first subgroup connects to a second line in said first group of longlines; the general output means of the first configurable logic block is couplable by a first programmable interconnect means in the first symmetrical distribution to the first line in said first group of longlines; the general output means of the second configurable logic block is couplable by a second programmable interconnect means in the first symmetrical distribution to the second line in said first group of longlines.

Claim 5

A programmable integrated circuit according to claim 1 wherein: each configurable logic block is defined within a perimeter having a plurality of CLB input terminals distributed thereabout in a generally uniform manner, the CLB input terminals including said longline input means.

Claim 6

A programmable integrated circuit according to claim 1 wherein: the perimeter of each configurable logic block further includes a plurality of CLB output terminals distributed thereabout in a generally uniform manner, the CLB output terminals including said general output means.

Claim 7

A programmable integrated circuit according to claim 1 formed on a die having four sides, wherein the number of configurable logic block in said integrated circuit is at least sixteen and said at least sixteen configurable logic blocks are symmetrically disposed on the die relative to the four sides of the die.

Claim 8

A programmable integrated circuit according to claim 6 wherein the number of configurable logic blocks in said integrated circuit is at least sixty-four.

Claim 9

A programmable integrated circuit comprising: (a) a plurality of programmably configurable logic blocks for carrying out program-defined logic functions; (b) a plurality of input/output blocks for providing an interface between the plurality of configurable logic blocks and points outside said integrated circuit, each of said input/output blocks having input means for inputting signals to the plurality of programmably configurable logic blocks, and output means for outputting signals from the plurality of programmably configurable logic blocks; and (c) a programmably configurable interconnect network for providing program-defined routing of signals between the plurality of programmably configurable logic blocks and the plurality of input/output blocks, wherein said configurable interconnect network includes: (c.1) a first group of at least four longlines, said first group of longlines extending by a first subset of at least four of the configurable logic blocks and extending to, and coupling to a corresponding first subset of at least two of the input/output blocks; and (c.2) a first symmetrical distribution of programmable interconnect means provided along the first group of longlines for providing program-defined coupling between respective combinations of more than one but not all of the first group of longlines and corresponding combinations of more than one but not all of the first subset of configurable logic blocks, the first symmetrical distribution of the programmable interconnect means being such that a substantially same signal propagation delay develops for each longline in said first group when coupling a corresponding one or more of the first subset of configurable logic blocks to a corresponding one or more of the first subset of input/output blocks.

Claim 10

A programmable integrated circuit comprising: (a) a plurality of programmably configurable logic blocks for carrying out program-defined logic functions; (b) a plurality of input/output blocks for providing an interface between the plurality of configurable logic blocks and points outside said integrated circuit, each of said input/output blocks having input means for inputting signals to the plurality of programmably configurable logic blocks, and output means for outputting signals from the plurality of programmably configurable logic blocks; and (c) a programmably configurable interconnect network for providing program-defined routing of signals between the plurality of programmably configurable logic blocks and the plurality of input/output blocks, wherein said configurable interconnect network includes: (c.1) a first group of at least four longlines, said first group of longlines extending by a first subset of at least four of the configurable logic blocks and extending to, and coupling to a corresponding first subset of at least two of the input/output blocks; and (c.2) a first symmetrical distribution of programmable interconnect means provided along the first group of longlines for providing program-defined coupling between respective combinations of more than one but not all of the first group of longlines and corresponding combinations of more than one but not all of the first subset of configurable logic blocks, the first symmetrical distribution of the programmable interconnect means being such that a substantially same signal propagation delay develops for each longline in said first group when coupling a corresponding one or more of the first subset of configurable logic blocks to a corresponding one or more of the first subset of input/output blocks.

Claim 11

A programmable integrated circuit according to claim 8 wherein said configurable interconnect network includes: (c.3) a second group of at least four longlines, said second group extending by said first subset of at least four of the configurable logic blocks and extending to, and coupling to a second subset of at least two of the input/output blocks, said second subset of input/output blocks being different than said first subset of input/output blocks; and (c.4) a second symmetrical distribution of programmable interconnect means provided along the second group of longlines for providing program-defined coupling between respective combinations of more than one but not all of the second group of longlines and corresponding combinations of more than one but not all of the first subset of configurable logic blocks, the second symmetrical distribution of the programmable interconnect means being such that a substantially same signal propagation delay develops for each longline in said second group when coupling a corresponding one or more of the first subset of configurable logic blocks to a corresponding one or more of the second subset of input/output blocks.

Claim 12

A programmable integrated circuit according to claim 9 wherein: said second symmetrical distribution of programmable interconnect means is substantially the same as said first symmetrical distribution of programmable interconnect means such that signals may be routed along either the first group of longlines or the second group of longlines with no substantial difference in propagation delay.

Claim 13

A programmable integrated circuit according to claim 10 wherein: said second group of longlines extends orthogonally relative to said first group of longlines.

Claim 14

A programmable integrated circuit according to claim 8 wherein said first subset of at least two of the input/output blocks includes: (c.1a) a programmably-configurable simple IOB; and (c.1b) a programmably-configurable complex IOB, the simple IOB having a tri-state output buffer for outputting signals to at least one of said first group of longlines, the complex IOB also having a tri-state output buffer for outputting signals to at least one of said first group of longlines, and the complex IOB further having register means for storing at least one of input and output signals passing through the input means of said complex IOB.

Claim 15

A programmable integrated circuit according to claim 8 wherein said first subset of input/output blocks has at least four input/output blocks.

Claim 16

A programmable integrated circuit according to claim 13 wherein said first subset of input/output blocks has at least eight input/output blocks.

Claim 17

A programmable integrated circuit according to claim 13 wherein: said first subset of input/output blocks is divided into first and second IOB groups each having a same number of input/output blocks, the first and second IOB groups being respectively positioned at opposed ends of the first group of longlines; and the first symmetrical distribution of programmable interconnect means is such that signals may be routed along the first group of longlines to either of the first and second IOB groups with no substantial difference in propagation delay.

Claim 18

A programmable integrated circuit according to claim 8 wherein: said first subset of input/output blocks is divided into first and second IOB groups, the first and second IOB groups being spaced apart from one another by more than half the length of the first group of longlines; and the first symmetrical distribution of programmable interconnect means is such that signals may be routed along the first group of longlines to either of the first and second IOB groups with no substantial difference in propagation delay.

Claim 19

A programmable integrated circuit according to claim 16 wherein: said first subset of configurable logic blocks is positioned along the first group of longlines approximately midway between the first and second IOB groups; said second group of longlines additionally extends by a second subset of configurable logic blocks; and the first symmetrical distribution of programmable interconnect means is such that signals may be routed along the first group of longlines either from the first subset of configurable logic blocks or from the second subset of configurable logic blocks to either of the first and second IOB groups with no substantial difference in propagation delay for any such permutation of signal routings.

Claim 20

A programmable integrated circuit according to claim 8 wherein the plurality of input/output blocks includes programmably-configurable input/output blocks.

Claim 21

A programmable integrated circuit according to claim 8 wherein each programmably-configurable input/output block includes a tri-state output buffer for outputting signals to at least one line of said first group of longlines, said tri-state output buffer having a tri-state control line driven by a programmably-defined tri-state control signal.

Claim 22

A programmable integrated circuit according to claim 19 wherein: each programmably-configurable input/output block further includes a programmably-configurable tri-state control multi-plexer having an output for generating said tri-state control signal and a plurality of inputs; at least one of said inputs of the tri-state control multiplexer being programmably-routed from a second group of longlines that are driven by at least one of the plurality of input/output blocks or one of the plurality of configurable logic blocks.