US5428800A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input/output (I/O) bidirectional buffer for interfacing I/O ports of a field programmable interconnection device with array ports of a cross-point switch
Assignee: RPX Corp
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Filing: 1992-10-13
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Granted: 1995-06-27
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Expires: 2012-10-13
Abstract
Abstract A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up. The bi-directional buffer includes a register for storing and reading out data representing successive logic states of a signal on the first bus, thereby providing a history of data appearing on the bus.
Inventors
- 👤 Wen-Jai Hsieh
- 👤 Yih-Chyun Jenq
- 👤 Chi-Song Horng
- 👤 Keith Lofstrom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:54
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017581; H03K19/01759
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
303 words
An apparatus for providing an interface between first and second port signals at first and second port terminals, respectively, the apparatus comprising: first driver means receiving first and second input signals for driving said first port signal to a first logic state in response to assertion of said first input signal and for driving said first port signal to a second logic state in response to assertion of said second input signal; second driver means receiving third and fourth input signals for driving said second port signal to a third logic state in response to assertion of a third input signal and for driving said second port signal to a fourth logic state in response to assertion of a fourth input signal; first single-shot means receiving said first input signal for asserting and then deasserting said second input signal in response to said first input signal; second single-shot means receiving said third input signal for asserting and then deasserting said fourth input signal in response to said third input signal; first logic means receiving said second port signal, said third input signal and said fourth input signal, for controlling assertion of said first input signal in response to logical combinations of states of said second port signal, said third input signal and said fourth input signal; second logic means receiving said first port signal, said first input signal and said second input signal, for controlling assertion of said third input signal in response to logical combinations of states of said first port signal, said first input signal and said second input signal; and means receiving said first port signal, for detecting successive logic states of said first port signal, for storing a plurality of data bits representing said successive logic states, and for reading out said plurality of data bits on a bus.
Claim 2
Independent Claim
303 words
An apparatus for providing an interface between first and second port signals at first and second port terminals, respectively, the apparatus comprising: first driver means receiving first and second input signals for driving said first port signal to a first logic state in response to assertion of said first input signal and for driving said first port signal to a second logic state in response to assertion of said second input signal; second driver means receiving third and fourth input signals for driving said second port signal to a third logic state in response to assertion of a third input signal and for driving said second port signal to a fourth logic state in response to assertion of a fourth input signal; first single-shot means receiving said first input signal for asserting and then deasserting said second input signal in response to said first input signal; second single-shot means receiving said third input signal for asserting and then deasserting said fourth input signal in response to said third input signal; first logic means receiving said second port signal, said third input signal and said fourth input signal, for controlling assertion of said first input signal in response to logical combinations of states of said second port signal, said third input signal and said fourth input signal; second logic means receiving said first port signal, said first input signal and said second input signal, for controlling assertion of said third input signal in response to logical combinations of states of said first port signal, said first input signal and said second input signal; and means receiving said first port signal, for detecting successive logic states of said first port signal, for storing a plurality of data bits representing said successive logic states, and for reading out said plurality of data bits on a bus.
Claim 3
Independent Claim
293 words
An apparatus for providing an interface between first and second port signals at first and second port terminals, respectively, in response to first and second control signals supplied as input to said apparatus, the apparatus comprising: first driver means receiving first and second input signals, for driving said first port signal to a first logic state in response to assertion of said first input signal and for driving said first port signal to a second logic state in response to assertion of said second input signal; second driver means receiving third and fourth input signals for driving said second port signal to a third logic state in response to assertion of a third input signal and for driving said second port signal to a fourth logic state in response to assertion of a fourth input signal; first single-shot means receiving said first input signal for asserting and then deasserting said second input signal in response to said first input signal; second single-shot means receiving said third input signal for asserting and then deasserting said fourth input signal in response to said third input signal; first logic means receiving said second port signal, said third input signal, said fourth input signal and said first control signal, for controlling assertion of said first input signal in response to logical combinations of states of said second port signal, said third input signal, said fourth input signal and said first control signal; and second logic means receiving said first port signal, said first input signal, said second input signal and said second control signal, for controlling assertion of said third input signal in response to logical combinations of states of said first port signal, said first input signal, said second input signal and said second control signal.
Claim 4
Independent Claim
293 words
An apparatus for providing an interface between first and second port signals at first and second port terminals, respectively, in response to first and second control signals supplied as input to said apparatus, the apparatus comprising: first driver means receiving first and second input signals, for driving said first port signal to a first logic state in response to assertion of said first input signal and for driving said first port signal to a second logic state in response to assertion of said second input signal; second driver means receiving third and fourth input signals for driving said second port signal to a third logic state in response to assertion of a third input signal and for driving said second port signal to a fourth logic state in response to assertion of a fourth input signal; first single-shot means receiving said first input signal for asserting and then deasserting said second input signal in response to said first input signal; second single-shot means receiving said third input signal for asserting and then deasserting said fourth input signal in response to said third input signal; first logic means receiving said second port signal, said third input signal, said fourth input signal and said first control signal, for controlling assertion of said first input signal in response to logical combinations of states of said second port signal, said third input signal, said fourth input signal and said first control signal; and second logic means receiving said first port signal, said first input signal, said second input signal and said second control signal, for controlling assertion of said third input signal in response to logical combinations of states of said first port signal, said first input signal, said second input signal and said second control signal.
Claim 5
Dependent Claim
45 words
The apparatus in accordance with claim 2 further comprising: data storage means for receiving and storing control data conveyed thereto on a bus; and means for generating said first and second control signals in response to said control data stored by said data storage means.
Claim 6
Dependent Claim
49 words
The apparatus in accordance with claim 2 further comprising means receiving said first port signal, for detecting successive logic states of said first port signal, for storing a plurality of data bits representing said successive logic states, and for reading out said plurality of data bits on a bus.
Claim 7
Dependent Claim
45 words
The apparatus in accordance with claim 4 further comprising: data storage means for receiving and storing control data conveyed thereto on said bus; and means for generating said first and second control signals in response to said control data stored by said data storage means.
Claim 8
Dependent Claim
64 words
The apparatus in accordance with claim 2 wherein said first logic means asserts said first input signal in delayed response to said logical combination of states of said second port signal, said third input signal, said fourth input signal and said first control signal, a duration of delay of said delayed response being determined by a delay signal supplied as input to said apparatus.
Claim 9
Dependent Claim
49 words
The apparatus in accordance with claim 6 further comprising: data storage means for receiving and storing control data conveyed thereto on a bus; and means for generating said first and second control signals and said delay signal in response to said control data stored by said data storage means.
Claim 10
Dependent Claim
49 words
The apparatus in accordance with claim 6 further comprising means receiving said first port signal, for detecting successive logic states of said first port signal, for storing a plurality of data bits representing said successive logic states, and for reading out said plurality of data bits on a bus.
Claim 11
Dependent Claim
49 words
The apparatus in accordance with claim 8 further comprising: data storage means for receiving and storing control data conveyed thereto on said bus; and means for generating said first and second control signals and said delay signal in response to said control data stored by said data storage means.
Claim 12
Independent Claim
286 words
An apparatus for providing an adjustably delayed interface between first and second port signals at first and second port terminals, respectively, the apparatus comprising: first driver means receiving first and second input signals, for driving said first port signal to a first logic state in response to assertion of said first input signal and for driving said first port signal to a second logic state in response to assertion of said second input signal; second driver means receiving third and fourth input signals for driving said second port signal to a third logic state in response to assertion of a third input signal and for driving said second port signal to a fourth logic state in response to assertion of a fourth input signal; first single-shot means receiving said first input signal for asserting and then deasserting said second input signal in response to said first input signal; second single-shot means receiving said third input signal for asserting and then deasserting said fourth input signal in response to said third input signal; first logic means receiving said second port signal, said third input signal, and said fourth input signal, and a delay control signal, for controlling assertion of said first input signal in adjustably delayed response to logical combinations of states of said second port signal, said third input signal, and said fourth input signal, a duration of delay of said response being determined by said delay control signal; and second logic means receiving said first port signal, said first input signal, and said second input signal for controlling assertion of said third input signal in response to logical combinations of states of said first port signal, said first input signal, and said second input signal.
Claim 13
Independent Claim
286 words
An apparatus for providing an adjustably delayed interface between first and second port signals at first and second port terminals, respectively, the apparatus comprising: first driver means receiving first and second input signals, for driving said first port signal to a first logic state in response to assertion of said first input signal and for driving said first port signal to a second logic state in response to assertion of said second input signal; second driver means receiving third and fourth input signals for driving said second port signal to a third logic state in response to assertion of a third input signal and for driving said second port signal to a fourth logic state in response to assertion of a fourth input signal; first single-shot means receiving said first input signal for asserting and then deasserting said second input signal in response to said first input signal; second single-shot means receiving said third input signal for asserting and then deasserting said fourth input signal in response to said third input signal; first logic means receiving said second port signal, said third input signal, and said fourth input signal, and a delay control signal, for controlling assertion of said first input signal in adjustably delayed response to logical combinations of states of said second port signal, said third input signal, and said fourth input signal, a duration of delay of said response being determined by said delay control signal; and second logic means receiving said first port signal, said first input signal, and said second input signal for controlling assertion of said third input signal in response to logical combinations of states of said first port signal, said first input signal, and said second input signal.
Claim 14
Dependent Claim
43 words
The apparatus in accordance with claim 10 further comprising: data storage means for receiving and storing control data conveyed thereto on a bus; and means for generating said delay control signal in response to said control data stored by said data storage means.
Claim 15
Dependent Claim
49 words
The apparatus in accordance with claim 10 further comprising means receiving said first port signal, for detecting successive logic states of said first port signal, for storing a plurality of data bits representing said successive logic states, and for reading out said plurality of data bits on a bus.
Claim 16
Dependent Claim
43 words
The apparatus in accordance with claim 12 further comprising: data storage means for receiving and storing control data conveyed thereto on said bus; and means for generating said delay control signal in response to said control data stored by said data storage means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |