US4144565A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input/output interface connector circuit for repowering and isolation
Assignee: International Business Machines Corp
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Filing: 1977-01-06
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Granted: 1979-03-13
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Expires: 1997-01-06
Abstract
Abstract In a data processing system which includes a base central processing unit, channel, and input/output (I/O) interface to which peripheral devices may be attached, a special attachment is disclosed. The attachment made to the base I/O interface includes connector circuitry which is required when the signals on the input/output interface must be repowered to peripheral devices in an expansion input/output unit, power isolation must be provided between a base data processing system and I/O expansion unit, or a remote peripheral device is to be attached to the base data processing system I/O interface. The connector circuit includes logic which responds to the normal I/O interface signals to energize drivers in the connector circuit to achieve repowering of signals on bidirectional signal lines and unidirectional signal lines.
Inventors
- 👤 Max A. Bouknecht
- 👤 Louis P. Vergari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:23
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
121 words
A data processing system input/output (I/O) interface connector circuit for controlling the interconnection of data, address, and control signal lines between a first I/O bus associated with a central processing unit including an I/O channel and attached peripheral devices, and a further I/O bus, comprising: bidirectional driver means interconnecting data and address lines of the first I/O bus and corresponding data and address lines of the further I/O bus; unidirectional driver means interconnecting control lines of the first and further I/O bus; and logic means, connected and responsive to predetermined signals being transferred between any peripheral device and the I/O channel, and connected to said bidirectional driver means, for controlling the direction of signal transfer on the data and address lines.
Claim 2
Dependent Claim
121 words
A data processing system input/output (I/O) interface connector circuit for controlling the interconnection of data, address, and control signal lines between a first I/O bus associated with a central processing unit including an I/O channel and attached peripheral devices, and a further I/O bus, comprising: bidirectional driver means interconnecting data and address lines of the first I/O bus and corresponding data and address lines of the further I/O bus; unidirectional driver means interconnecting control lines of the first and further I/O bus; and logic means, connected and responsive to predetermined signals being transferred between any peripheral device and the I/O channel, and connected to said bidirectional driver means, for controlling the direction of signal transfer on the data and address lines.
Claim 3
Dependent Claim
102 words
A connector circuit in accordance with claim 1 wherein each said bidirectional driver means includes: a first driver for generating signals on the further I/O bus; a second driver for generating signals on the first I/O bus; a first gate connected for enabling said first driver, and connected and responsive to signals on the first I/O bus and said logic means; a second gate connected for enabling said second driver, and connected and responsive to signals on the further I/O bus and said logic means; and said logic means includes means for selectively rendering either said first or said second gate effective.
Claim 4
Dependent Claim
40 words
A connector circuit is accordance with claim 2 wherein: said second gate is connected and responsive to a predetermined signal on a predetermined one of the unidirectional control signal lines of the further bus for rendering said second gate inoperative.
Claim 5
Dependent Claim
142 words
A connector circuit in accordance with claim 1 wherein certain of the peripheral devices are directly attached to the first I/O bus in a multi-drop configuration and include interface capture logic responding to a poll signal from the I/O channel to either serially propagate the poll signal to a succeeding peripheral device or degate the poll signal to capture use of the I/O bus, and at least one peripheral device is directly attached to the further I/O bus, the connector circuit further including: interface capture logic including means connected and responsive to the presence or absence of a request signal from the at least one peripheral device to render said interface capture logic effective to degate or propagate, respectively, the poll signal; and means directly connecting said interface capture logic to certain of the control signal lines of the first I/O bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-12 | 1982-09-11 | 1983-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-12 | 1986-09-11 | 1987-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-12 | 1990-09-11 | 1991-03-13 | $7700.00 | Window Closed / Lapsed |