US5363494A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus interface circuit for connecting bus lines having different bit ranges
Assignee: Toshiba Corp
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Filing: 1992-10-22
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Granted: 1994-11-08
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Expires: 2012-10-22
Abstract
Abstract A first bus wiring line to which a plurality of first circuits each having the same bit range are connected, a second bus wiring line to which a plurality of second circuits each having a bit range smaller than that of each of the first circuits are connected, and a bus interface circuit having a buffer circuit connected between a portion of the first bus wiring line and the second bus wiring line and a dummy buffer circuit connected to the remaining portion of the first bus wiring line are arranged in an integrated circuit. Fox this reason, when a plurality of circuits having different bit ranges are connected to the bus wiring lines, the loads of the bus wiring lines can be made uniform, and a data transfer operation through the bus lines can be performed at a high speed. The operating frequency of a clock can be increased, and the performance of the system can be improved.
Inventors
- 👤 Tsuneaki Kudou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 00:30
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
153 words
A bus system of semiconductor device comprising: a plurality of bus wiring lines, each having different predetermined bit ranges, at least two bus wiring lines of which are connected to each other; and a plurality of interface circuits, each having a buffer circuit which has a bit range equal to the lower bit range of the predetermined bit ranges of said at least two bus wiring lines, and which is connected between said at least two bus wiring lines, and a dummy buffer circuit which has a bit range equal to the difference between the bit range of said at least two bus wiring lines, and which is connected to a portion of said bus wiring line having the larger bit range of said at least two bus wiring lines, said portion of said bus wiring line having the larger bit range being a portion to which said buffer circuit is not connected.
Claim 2
Dependent Claim
153 words
A bus system of semiconductor device comprising: a plurality of bus wiring lines, each having different predetermined bit ranges, at least two bus wiring lines of which are connected to each other; and a plurality of interface circuits, each having a buffer circuit which has a bit range equal to the lower bit range of the predetermined bit ranges of said at least two bus wiring lines, and which is connected between said at least two bus wiring lines, and a dummy buffer circuit which has a bit range equal to the difference between the bit range of said at least two bus wiring lines, and which is connected to a portion of said bus wiring line having the larger bit range of said at least two bus wiring lines, said portion of said bus wiring line having the larger bit range being a portion to which said buffer circuit is not connected.
Claim 3
Dependent Claim
34 words
A system according to claim 1, wherein a plurality of circuits having bit ranges equal to the bit ranges of said bus wiring lines are connected to said plurality of bus wiring lines, respectively.
Claim 4
Dependent Claim
47 words
A system according to claim 2, wherein said dummy buffer circuit has the dummy bit count for supplying the same fan-in and fan-out counts as those of said plurality of circuits to a bus wiring line of a larger bit range in said two bus wiring lines.
Claim 5
Dependent Claim
20 words
A system according to claim 1, wherein said buffer circuit of said bus interface circuit is a bidirectional buffer circuit.
Claim 6
Dependent Claim
26 words
A system according to claim 1, wherein said plurality of bus wiring lines and said plurality of interface circuits are formed in a semiconductor integrated circuit.
Claim 7
Dependent Claim
13 words
A system according to claim 1, wherein said semiconductor device is a microprocessor.
Claim 8
Dependent Claim
177 words
A bus system of a semiconductor device comprising: a first bus wiring line to which a plurality of first circuits, each having the same bit range are connected, said first bus wiring line consisting of a first portion and a second portion; a second bus wiring line to which a plurality of second circuits, each having a bit range smaller than that of each of said first circuits are connected, the bit range of said second bus wiring line being equal to that of said first portion of said first bus wiring line; and a bus interface circuit having a buffer circuit connected between said first portion of said first bus wiring line and said second bus wiring line, and a dummy buffer circuit which has a bit range equal to the difference between the bit ranges of said first and second bus wiring lines and which is connected to said second portion of said first bus wiring line to provide said bus interface circuit with a load equal to that of each of said first circuits.
Claim 9
Dependent Claim
177 words
A bus system of a semiconductor device comprising: a first bus wiring line to which a plurality of first circuits, each having the same bit range are connected, said first bus wiring line consisting of a first portion and a second portion; a second bus wiring line to which a plurality of second circuits, each having a bit range smaller than that of each of said first circuits are connected, the bit range of said second bus wiring line being equal to that of said first portion of said first bus wiring line; and a bus interface circuit having a buffer circuit connected between said first portion of said first bus wiring line and said second bus wiring line, and a dummy buffer circuit which has a bit range equal to the difference between the bit ranges of said first and second bus wiring lines and which is connected to said second portion of said first bus wiring line to provide said bus interface circuit with a load equal to that of each of said first circuits.
Claim 10
Dependent Claim
38 words
A system according to claim 7, wherein said buffer circuit has a bit range equal to a bit range of a bus wiring line of a smaller predetermined bit range in said first and second bus wiring lines.
Claim 11
Dependent Claim
50 words
A system according to claim 7, wherein said dummy buffer circuit has the dummy bit count for supplying the same fan-in and fan-out counts as those of said plurality of first circuits to a bus wiring line of a larger bit range in said first and second bus wiring lines.
Claim 12
Dependent Claim
20 words
A system according to claim 7, wherein said buffer circuit of said bus interface circuit is a bidirectional buffer circuit.
Claim 13
Dependent Claim
24 words
A system according to claim 7, wherein said plurality of bus wiring lines and said interface circuit are formed in a semiconductor integrated circuit.
Claim 14
Dependent Claim
13 words
A system according to claim 7, wherein said semiconductor device is a microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-07 | 1998-05-09 | 1998-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-07 | 2002-05-09 | 2002-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-07 | 2006-05-09 | 2006-11-08 | $7700.00 | Window Closed / Lapsed |