US5942919A
Expired / Lapsed
US
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Differential receiver including an enable circuit
Assignee: Sun Microsystems Inc
•
Filing: 1997-06-25
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Granted: 1999-08-24
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Expires: 2017-06-25
Abstract
Abstract A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.
Inventors
- 👤 Michael A. Ang
- 👤 Alexander D. Taylor
- 👤 Jonathan E. Starr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:35
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113
Claims Analysis
Total Claims: 54
Claim 1
Independent Claim
342 words
A differential receiver comprising a first pair of transistors, each of the first pair of transistors including a drain, a source and a gate, the source of one of the first pair of transistors being coupled to the drain of another of the first pair of transistors, the drain of the one of the first pair of transistors being coupled to a first node, the gate of the one of the first pair of transistors being coupled to a node enable signal, and the gate of the another of the first pair of transistors being coupled to a reference voltage, the first pair of transistors providing a voltage at the first node indicative of the reference voltage when the node enable signal is active; a second pair of transistors, each of the second pair of transistors including a drain, a source and a gate, the source of one of the second pair of transistors being coupled to the drain of another of the second pair of transistors, the drain of the one of the second pair of transistors being coupled to a second node, the gate of the one of the second pair of transistors being coupled to the node enable signal, and the gate of the another of the second pair of transistors being coupled to an input signal, the second pair of transistors providing a voltage at the second node indicative of the voltage of the input signal when the node enable signal is active; a resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active and the node enable signal is active; and, an enable circuit, the enable circuit receiving the clock signal and an input enable signal, the clock signal having an edge and providing the node enable signal having an edge, the edge of the node enable signal being delayed relative to the edge of the clock signal.
Claim 2
Dependent Claim
342 words
A differential receiver comprising a first pair of transistors, each of the first pair of transistors including a drain, a source and a gate, the source of one of the first pair of transistors being coupled to the drain of another of the first pair of transistors, the drain of the one of the first pair of transistors being coupled to a first node, the gate of the one of the first pair of transistors being coupled to a node enable signal, and the gate of the another of the first pair of transistors being coupled to a reference voltage, the first pair of transistors providing a voltage at the first node indicative of the reference voltage when the node enable signal is active; a second pair of transistors, each of the second pair of transistors including a drain, a source and a gate, the source of one of the second pair of transistors being coupled to the drain of another of the second pair of transistors, the drain of the one of the second pair of transistors being coupled to a second node, the gate of the one of the second pair of transistors being coupled to the node enable signal, and the gate of the another of the second pair of transistors being coupled to an input signal, the second pair of transistors providing a voltage at the second node indicative of the voltage of the input signal when the node enable signal is active; a resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active and the node enable signal is active; and, an enable circuit, the enable circuit receiving the clock signal and an input enable signal, the clock signal having an edge and providing the node enable signal having an edge, the edge of the node enable signal being delayed relative to the edge of the clock signal.
Claim 3
Dependent Claim
26 words
The differential receiver of claim 1, wherein the resolving circuit includes a first inverter; and a second inverter, the first and second inverters being cross coupled.
Claim 4
Dependent Claim
124 words
The differential receiver of claim 2 wherein the first inverter includes first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain; the second inverter includes first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain; the drains of the first and second transistors of the first inverter are coupled to the gates of the first and second transistors of the second inverter and to the first node; and the drains of the first and second transistors of the second inverter are coupled to the gates of the first and second transistors of the first inverter and to the second node.
Claim 5
Dependent Claim
48 words
The differential receiver of claim 3 wherein the source of one of the first and second transistors of the first inverter is coupled to the clock signal; and the source of one of the first and second transistors of the second inverter is coupled to the clock signal.
Claim 6
Dependent Claim
40 words
The differential receiver of claim 4 wherein the one of the first and second transistors of the first inverter is an NMOS transistor; and the one of the first and second transistors of the second inverter is an NMOS transistor.
Claim 7
Dependent Claim
48 words
The differential receiver of claim 4 wherein the source of another of the first and second transistors of the first inverter is coupled to a fixed voltage; and the source of another of the first and second transistors of the second inverter is coupled to a fixed voltage.
Claim 8
Dependent Claim
12 words
The differential receiver of claim 6 wherein the fixed voltage is ground.
Claim 9
Dependent Claim
40 words
The differential receiver of claim 6 wherein the another of the first and second transistors of the first inverter is a P-channel transistor; and the another of the first and second transistors of the second inverter is a P-channel transistor.
Claim 10
Dependent Claim
69 words
The differential receiver of claim 1 further comprising a latching circuit coupled to the resolving circuit via the first and second nodes, the latching circuit providing an output signal indicating which of the first and second nodes has a higher voltage, the latching circuit holding the state of the output signal indicating which of the first and second nodes has a higher voltage when the clock signal becomes inactive.
Claim 11
Dependent Claim
26 words
The differential receiver of claim 9, wherein the latching circuit includes a first inverter; and a second inverter, the first and second inverters being cross coupled.
Claim 12
Dependent Claim
124 words
The differential receiver of claim 10 wherein the first inverter includes first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain; the second inverter includes first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain; the drains of the first and second transistors of the first inverter are coupled to the gates of the first and second transistors of the second inverter and to the first node; and the drains of the first and second transistors of the second inverter are coupled to the gates of the first and second transistors of the first inverter and to the second node.
Claim 13
Dependent Claim
47 words
The differential receiver of claim 11 wherein the source of one of the first and second transistors of first inverter is coupled to a voltage source; and the source of one of the first and second transistors of the second inverter is coupled to the voltage source.
Claim 14
Dependent Claim
43 words
The differential receiver of claim 12 wherein the source of another of the first and second transistors of first inverter is coupled to ground; and the source of another of the first and second transistors of the second inverter is coupled to ground.
Claim 15
Dependent Claim
42 words
The differential receiver of claim 10 wherein the latching circuit includes an output-stage circuit having first and second output-stage portions, the output-stage portions determining the states of the first and second inverters when one of the first and second nodes is active.
Claim 16
Dependent Claim
33 words
The differential receiver of claim 1 further comprising: an equalization circuit coupled between the first and second nodes, the equalization circuit equalizing the first and second nodes when the clock signal is inactive.
Claim 17
Dependent Claim
38 words
The differential receiver of claim 1 wherein the enable circuit includes a transmission gate, the transmission gate receiving the clock signal and providing a delayed clock signal, the enable signal being provided based upon the delayed clock signal.
Claim 18
Dependent Claim
46 words
The differential receiver of claim 1 wherein the enable circuit includes a logic gate, the logic gate being coupled to receive the clock signal as well as an input enable signal, the logic gate providing the node enable signal when the input enable signal is active.
Claim 19
Dependent Claim
200 words
A differential receiver comprising: a first variable resistor having a first resistance value, the first variable resistor being coupled between a first node and a fixed voltage, the first resistance value of the first variable resistor being controlled by a reference voltage, the first variable resistor providing a voltage at the first node indicative of the reference voltage; a second variable resistor having a second resistance value, the second variable resistor being coupled between a second node and the fixed voltage, the second resistance value of the second variable resistor being controlled by an input signal, the second variable resistor providing a voltage at the second node indicative of the input signal; a resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active; and, an enable circuit, the enable circuit receiving the clock signal and an input enable signal, the clock signal having an edge and providing the node enable signal having an edge, the edge of the node enable signal being delayed relative to the edge of the clock signal.
Claim 20
Dependent Claim
200 words
A differential receiver comprising: a first variable resistor having a first resistance value, the first variable resistor being coupled between a first node and a fixed voltage, the first resistance value of the first variable resistor being controlled by a reference voltage, the first variable resistor providing a voltage at the first node indicative of the reference voltage; a second variable resistor having a second resistance value, the second variable resistor being coupled between a second node and the fixed voltage, the second resistance value of the second variable resistor being controlled by an input signal, the second variable resistor providing a voltage at the second node indicative of the input signal; a resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active; and, an enable circuit, the enable circuit receiving the clock signal and an input enable signal, the clock signal having an edge and providing the node enable signal having an edge, the edge of the node enable signal being delayed relative to the edge of the clock signal.
Claim 21
Dependent Claim
12 words
The differential receiver of claim 18 wherein the fixed voltage is ground.
Claim 22
Dependent Claim
26 words
The differential receiver of claim 18, wherein the resolving circuit includes a first inverter; and a second inverter, the first and second inverters being cross coupled.
Claim 23
Dependent Claim
124 words
The differential receiver of claim 20 wherein the first inverter includes first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain; the second inverter includes first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain; the drains of the first and second transistors of the first inverter are coupled to the gates of the first and second transistors of the second inverter and to the first node; and the drains of the first and second transistors of the second inverter are coupled to the gates of the first and second transistors of the first inverter and to the second node.
Claim 24
Dependent Claim
47 words
The differential receiver of claim 21 wherein the source of one of the first and second transistors of first inverter is coupled to the clock signal; and the source of one of the first and second transistors of the second inverter is coupled to the clock signal.
Claim 25
Dependent Claim
40 words
The differential receiver of claim 22 wherein the one of the first and second transistors of the first inverter is an NMOS transistor; and the one of the first and second transistors of the second inverter is an NMOS transistor.
Claim 26
Dependent Claim
48 words
The differential receiver of claim 22 wherein the source of another of the first and second transistors of the first inverter is coupled to a fixed voltage; and the source of another of the first and second transistors of the second inverter is coupled to a fixed voltage.
Claim 27
Dependent Claim
12 words
The differential receiver of claim 24 wherein the fixed voltage is ground.
Claim 28
Dependent Claim
40 words
The differential receiver of claim 24 wherein the another of the first and second transistors of the first inverter is a P-channel transistor; and the another of the first and second transistors of the second inverter is a P-channel transistor.
Claim 29
Dependent Claim
69 words
The differential receiver of claim 18 further comprising: a latching circuit coupled to the resolving circuit via the first and second nodes, the latching circuit providing an output signal indicating which of the first and second nodes has a higher voltage, the latching circuit holding the state of the output signal indicating which of the first and second nodes has a higher voltage when the clock signal becomes inactive.
Claim 30
Dependent Claim
26 words
The differential receiver of claim 27, wherein the latching circuit includes a first inverter; and a second inverter, the first and second inverters being cross coupled.
Claim 31
Dependent Claim
124 words
The differential receiver of claim 28 wherein the first inverter includes first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain; the second inverter includes first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain; the drains of the first and second transistors of the first inverter are coupled to the gates of the first and second transistors of the second inverter and to the first node; and the drains of the first and second transistors of the second inverter are coupled to the gates of the first and second transistors of the first inverter and to the second node.
Claim 32
Dependent Claim
47 words
The differential receiver of claim 29 wherein the source of one of the first and second transistors of first inverter is coupled to a voltage source; and the source of one of the first and second transistors of the second inverter is coupled to the voltage source.
Claim 33
Dependent Claim
43 words
The differential receiver of claim 30 wherein the source of another of the first and second transistors of first inverter is coupled to ground; and the source of another of the first and second transistors of the second inverter is coupled to ground.
Claim 34
Dependent Claim
73 words
The differential receiver of claim 28 wherein the latching circuit includes an output-stage circuit having first and second output-stage portions, the first output-stage portion being coupled to the first inverter and to the first node and the second output-stage portion being coupled to the second inverter and to the second node, the output-stage portions determining the states of the first and second inverters when one of the first and second nodes is active.
Claim 35
Dependent Claim
33 words
The differential receiver of claim 18 further comprising: an equalization circuit coupled between the first and second nodes, the equalization circuit equalizing the first and second nodes when the clock signal is inactive.
Claim 36
Dependent Claim
38 words
The differential receiver of claim 18 wherein the enable circuit includes a transmission gate, the transmission gate receiving the clock signal and providing a delayed clock signal, the enable signal being provided based upon the delayed clock signal.
Claim 37
Dependent Claim
46 words
The differential receiver of claim 18 wherein the enable circuit includes a logic gate, the logic gate being coupled to receive the clock signal as well as an input enable signal, the logic gate providing the node enable signal when the input enable signal is active.
Claim 38
Dependent Claim
286 words
A differential receiver comprising: a first variable resistor having a first resistance value, the first variable resistor being coupled between a first node and a fixed voltage, the first resistance value of the first variable resistor being controlled by a reference voltage, the first variable resistor providing a voltage at the first node indicative of the reference voltage; a second variable resistor having a second resistance value, the second variable resistor being coupled between a second node and the fixed voltage, the second resistance value of second variable resistor being controlled by an input signal, the second variable resistor providing a voltage at the second node indicative of the input signal; and a resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active; a latching circuit coupled to the resolving circuit via the first and second nodes, the latching circuit providing an output signal indicating which of the first and second nodes has a higher voltage, the latching circuit holding the state of the output signal indicating which of the first and second nodes has a higher voltage when the clock signal becomes inactive; an equalization circuit coupled between the first and second nodes, the equalization circuit equalizing the first and second nodes when the clock signal is inactive; and an enable circuit, the enable circuit receiving the clock signal and an input enable signal, the clock signal having an edge and providing a node enable signal having an edge, the edge of the node enable signal being delayed relative to the edge of the clock signal.
Claim 39
Dependent Claim
286 words
A differential receiver comprising: a first variable resistor having a first resistance value, the first variable resistor being coupled between a first node and a fixed voltage, the first resistance value of the first variable resistor being controlled by a reference voltage, the first variable resistor providing a voltage at the first node indicative of the reference voltage; a second variable resistor having a second resistance value, the second variable resistor being coupled between a second node and the fixed voltage, the second resistance value of second variable resistor being controlled by an input signal, the second variable resistor providing a voltage at the second node indicative of the input signal; and a resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active; a latching circuit coupled to the resolving circuit via the first and second nodes, the latching circuit providing an output signal indicating which of the first and second nodes has a higher voltage, the latching circuit holding the state of the output signal indicating which of the first and second nodes has a higher voltage when the clock signal becomes inactive; an equalization circuit coupled between the first and second nodes, the equalization circuit equalizing the first and second nodes when the clock signal is inactive; and an enable circuit, the enable circuit receiving the clock signal and an input enable signal, the clock signal having an edge and providing a node enable signal having an edge, the edge of the node enable signal being delayed relative to the edge of the clock signal.
Claim 40
Dependent Claim
12 words
The differential receiver of claim 36 wherein the fixed voltage is ground.
Claim 41
Dependent Claim
26 words
The differential receiver of claim 36, wherein the resolving circuit includes a first inverter; and a second inverter, the first and second inverters being cross coupled.
Claim 42
Dependent Claim
124 words
The differential receiver of claim 38 wherein the first inverter includes first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain; the second inverter includes first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain; the drains of the first and second transistors of the first inverter are coupled to the gates of the first and second transistors of the second inverter and to the first node; and the drains of the first and second transistors of the second inverter are coupled to the gates of the first and second transistors of the first inverter and to the second node.
Claim 43
Dependent Claim
48 words
The differential receiver of claim 39 wherein the source of one of the first and second transistors of the first inverter is coupled to the clock signal; and the source of one of the first and second transistors of the second inverter is coupled to the clock signal.
Claim 44
Dependent Claim
40 words
The differential receiver of claim 40 wherein the one of the first and second transistors of the first inverter is an NMOS transistor; and the one of the first and second transistors of the second inverter is an NMOS transistor.
Claim 45
Dependent Claim
48 words
The differential receiver of claim 40 wherein the source of another of the first and second transistors of the first inverter is coupled to the fixed voltage; and the source of another of the first and second transistors of the second inverter is coupled to the fixed voltage.
Claim 46
Dependent Claim
12 words
The differential receiver of claim 42 wherein the fixed voltage is ground.
Claim 47
Dependent Claim
40 words
The differential receiver of claim 42 wherein the another of the first and second transistors of the first inverter is a P-channel transistor; and the another of the first and second transistors of the second inverter is a P-channel transistor.
Claim 48
Dependent Claim
26 words
The differential receiver of claim 36, wherein the latching circuit includes a first inverter; and a second inverter, the first and second inverters being cross coupled.
Claim 49
Dependent Claim
124 words
The differential receiver of claim 45 wherein the first inverter includes first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain; the second inverter includes first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain; the drains of the first and second transistors of the first inverter are coupled to the gates of the first and second transistors of the second inverter and to the first node; and the drains of the first and second transistors of the second inverter are coupled to the gates of the first and second transistors of the first inverter and to the second node.
Claim 50
Dependent Claim
48 words
The differential receiver of claim 46 wherein the source of one of the first and second transistors of the first inverter is coupled to a voltage source; and the source of one of the first and second transistors of the second inverter is coupled to the voltage source.
Claim 51
Dependent Claim
44 words
The differential receiver of claim 47 wherein the source of another of the first and second transistors of the first inverter is coupled to ground; and the source of another of the first and second transistors of the second inverter is coupled to ground.
Claim 52
Dependent Claim
73 words
The differential receiver of claim 40 wherein the latching circuit includes an output-stage circuit having first and second output-stage portions, the first output-stage portion being coupled to the first inverter and to the first node and the second output-stage portion being coupled to the second inverter and to the second node, the output-stage portions determining the states of the first and second inverters when one of the first and second nodes is active.
Claim 53
Dependent Claim
38 words
The differential receiver of claim 36 wherein the enable circuit includes a transmission gate, the transmission gate receiving the clock signal and providing a delayed clock signal, the enable signal being provided based upon the delayed clock signal.
Claim 54
Dependent Claim
46 words
The differential receiver of claim 36 wherein the enable circuit includes a logic gate, the logic gate being coupled to receive the clock signal as well as the input enable signal, the logic gate providing the node enable signal when the input enable signal is active.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |