US4937479A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data latch circuit with improved data write control function
Assignee: NEC Corp
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Filing: 1989-01-30
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Granted: 1990-06-26
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Expires: 2009-01-30
Abstract
Abstract A latch circuit includes a current source, and a flip-flop amplifier circuit having a pair of first and second input terminals for comparing a reference voltage and an external input voltage with each other and amplifying the voltage difference therebetween in response to inputting of an activating signal. A first transistor has a source terminal, a drain terminal connected to the first input terminal of the flip-flop amplification circuit, and a gate terminal receptive of the external input voltage. A second transistor has a source terminal connected to the source terminal of the first transistor, a drain terminal connected to the second input terminal of the flip-flop amplification circuit, and a gate terminal receptive of the reference voltage. A pair of gate elements are connected in series between the sources of the first and second transistors and the current source, and operate after the completion of amplification of the voltage difference in the flip-flop amplifier circuit for cutting off a drain current flowing through the first and second transistors so as to enable the flip-flop amplifier circuit to latch the external input voltage.
Inventors
- 👤 Katsuji Hoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 00:59
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356034; H03K3/356043
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
209 words
A latch circuit comprising a flip-flop circuit having a pair of first and second input nodes and first and second output nodes and a first terminal receiving an input signal, a second terminal receiving a reference voltage, a first transistor connected between said first input hode and a common node, a second transistor connected between said second input node and said common node, first means for connecting said first terminal to a gate of said first transistor, second means for connecting said second terminal to a gate of said second transistor, a series circuit of third and fourth transistors connected between said common node and a source voltage source, third means connected between said first output node and a gate of said third transistor for controlling said third transistor in response to a level at said first output node, fourth means connected between said second node and a gate of said fourth transistor and controlling said fourth transistor in response to a level at said second output node, said first and second output nodes being charged to an active level before amplifying operation of said flip-flop circuit and one of said first and second output nodes being changed to an inactive level after amplifying operation of said flip-flop circuit.
Claim 2
Dependent Claim
209 words
A latch circuit comprising a flip-flop circuit having a pair of first and second input nodes and first and second output nodes and a first terminal receiving an input signal, a second terminal receiving a reference voltage, a first transistor connected between said first input hode and a common node, a second transistor connected between said second input node and said common node, first means for connecting said first terminal to a gate of said first transistor, second means for connecting said second terminal to a gate of said second transistor, a series circuit of third and fourth transistors connected between said common node and a source voltage source, third means connected between said first output node and a gate of said third transistor for controlling said third transistor in response to a level at said first output node, fourth means connected between said second node and a gate of said fourth transistor and controlling said fourth transistor in response to a level at said second output node, said first and second output nodes being charged to an active level before amplifying operation of said flip-flop circuit and one of said first and second output nodes being changed to an inactive level after amplifying operation of said flip-flop circuit.
Claim 3
Dependent Claim
172 words
A latch circuit comprising a flip-flop circuit for comparing a reference voltage outputted from a reference voltage generating circuit with an external input voltage in response to inputting of an activating signal and for amplifying the compared result, a first transistor having a drain terminal connected to a first input terminal of the flip-flop circuit, and a gate terminal connected to receive the external input voltage; a second transistor having a drain terminal connected to a second input terminal of the flip-flop circuit, a gate terminal connected to receive the reference voltage, and a source terminal connected to a source terminal of the second transistor; a first gate element having a terminal connected to a power source and being controlled by a control signal produced within the flip-flop circuit; and a second gate element having a terminal connected to the source terminals of the first and second transistors and another terminal connected to another terminal of the first gate element, and being controlled by another control signal produced within the flip-flop circuit.
Claim 4
Dependent Claim
172 words
A latch circuit comprising a flip-flop circuit for comparing a reference voltage outputted from a reference voltage generating circuit with an external input voltage in response to inputting of an activating signal and for amplifying the compared result, a first transistor having a drain terminal connected to a first input terminal of the flip-flop circuit, and a gate terminal connected to receive the external input voltage; a second transistor having a drain terminal connected to a second input terminal of the flip-flop circuit, a gate terminal connected to receive the reference voltage, and a source terminal connected to a source terminal of the second transistor; a first gate element having a terminal connected to a power source and being controlled by a control signal produced within the flip-flop circuit; and a second gate element having a terminal connected to the source terminals of the first and second transistors and another terminal connected to another terminal of the first gate element, and being controlled by another control signal produced within the flip-flop circuit.
Claim 5
Dependent Claim
16 words
A latch circuit according to claim 2; wherein each gate element comprises an enhancement type transistor.
Claim 6
Dependent Claim
19 words
A latch circuit according to claim 2; including a current-amplifier circuit for current-amplifying an output from the flip-flop circuit.
Claim 7
Dependent Claim
27 words
A latch circuit according to claim 4; wherein the current-amplifier circuit comprises a pair of two series-connected transistors, the pair being connected in parallel to each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-25 | 1993-12-25 | 1994-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-25 | 1997-12-25 | 1998-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-25 | 2001-12-25 | 2002-06-26 | $7700.00 | Window Closed / Lapsed |