US5942914A
Expired / Lapsed
US
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PLD with split multiplexed inputs from global conductors
Assignee: Altera Corp
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Filing: 1997-06-19
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Granted: 1999-08-24
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Expires: 2017-06-19
Abstract
Abstract An improved multiplexer arrangement for connecting global conductors to logic array block (LAB) inputs. A single connection connects a particular global conductor to an input path to LABs on both sides of the interconnect region in a folded LAB architecture. The number of connections to the global conductors is thus reduced, reducing the number of transistors needed to make those connections and the corresponding loading of the global conductors. The connections to two paths are part of a first level multiplexer. A second-level multiplexer connected to each LAB line is also provided to add back some of the flexibility lost by having each global conductor connection connect to two paths. The invention cuts the number of transistors needed to connect to the global conductors in half, while adding some transistors for the second-level multiplexers, with a net reduction in connection transistors of about 1/3.
Inventors
- 👤 Srinivas Reddy
- 👤 Christopher Lane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1733; H03K19/1737; H03K19/17724; H03K19/17728; H03K19/1778
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
140 words
A programmable logic device comprising: a plurality of global conductors; a plurality of logic array blocks, each of which has a plurality of inputs and at least one output, a first set of logic array blocks being on a first side of said global conductors, a second set of logic array blocks being on a second side of said global conductors; a plurality of multiplexers, each multiplexer having a plurality of inputs for coupling to different ones of said global conductors and an output coupled to one of said logic array block inputs; wherein a single connection connects one of said global conductors to both an input of a first multiplexer connected to a first logic array block in said first set, and an input of a second multiplexer connected to a first logic array block in said second set.
Claim 2
Dependent Claim
140 words
A programmable logic device comprising: a plurality of global conductors; a plurality of logic array blocks, each of which has a plurality of inputs and at least one output, a first set of logic array blocks being on a first side of said global conductors, a second set of logic array blocks being on a second side of said global conductors; a plurality of multiplexers, each multiplexer having a plurality of inputs for coupling to different ones of said global conductors and an output coupled to one of said logic array block inputs; wherein a single connection connects one of said global conductors to both an input of a first multiplexer connected to a first logic array block in said first set, and an input of a second multiplexer connected to a first logic array block in said second set.
Claim 3
Dependent Claim
14 words
A digital system comprising a programmable logic device as set forth in claim 1.
Claim 4
Dependent Claim
88 words
The programmable logic device of claim 1 wherein there are M global conductors, N inputs to each of said first logic array blocks, and wherein said first and second multiplexers are second-level multiplexers, and further comprising a plurality of first-level multiplexers coupling said global conductors to said first and second-level multiplexers, each of said first-level multiplexers having (M*K)/(N*S) global conductor inputs, where S is the number of inputs into each second-level multiplexer, and K is the number ways into a logic array block from a given global conductor.
Claim 5
Dependent Claim
19 words
The programmable logic device of claim 3 wherein S=2, with two first level multiplexers connected to each second-level multiplexer.
Claim 6
Dependent Claim
19 words
The programmable logic device of claim 3 wherein S=4, with four first level multiplexers connected to each second-level multiplexer.
Claim 7
Dependent Claim
19 words
The programmable logic device of claim 5 wherein each of said first level multiplexers is a M/(N*2) input multiplexer.
Claim 8
Dependent Claim
46 words
The programmable logic device of claim 1 wherein said single connection also connects to an input of a third multiplexer connected to said first logic array block in said first set, and a fourth multiplexer connected to said first logic array block in said second set.
Claim 9
Dependent Claim
17 words
The programmable logic device of claim 7 wherein said first and third multiplexers are adjacent each other.
Claim 10
Dependent Claim
21 words
The programmable logic device of claim 1 further comprising a separate RAM bit control input coupled to each of said multiplexers.
Claim 11
Dependent Claim
17 words
The programmable logic device of claim 1 wherein said device is integrated on a single silicon chip.
Claim 12
Dependent Claim
203 words
A programmable logic device comprising: a plurality of global conductors; a plurality of logic array blocks, each of which has a plurality of inputs and at least one output, a first set of logic array blocks being on a first side of said global conductors, a second set of logic array blocks being on a second side of said global conductors; a plurality of multiplexers, each multiplexer having a plurality of inputs for coupling to different ones of said global conductors and an output coupled to one of said logic array block inputs; wherein a single connection connects one of said global conductors to both an input of a first multiplexer connected to a first logic array block in said first set, and an input of a second multiplexer connected to a first logic array block in said second set, said first and second logic array blocks being opposite each other; wherein said single connection also connects to an input of a third multiplexer connected to said first logic array block in said first set, and a fourth multiplexer connected to said first logic array block in said second set; and a separate RAM bit control input coupled to each of said multiplexers.
Claim 13
Dependent Claim
203 words
A programmable logic device comprising: a plurality of global conductors; a plurality of logic array blocks, each of which has a plurality of inputs and at least one output, a first set of logic array blocks being on a first side of said global conductors, a second set of logic array blocks being on a second side of said global conductors; a plurality of multiplexers, each multiplexer having a plurality of inputs for coupling to different ones of said global conductors and an output coupled to one of said logic array block inputs; wherein a single connection connects one of said global conductors to both an input of a first multiplexer connected to a first logic array block in said first set, and an input of a second multiplexer connected to a first logic array block in said second set, said first and second logic array blocks being opposite each other; wherein said single connection also connects to an input of a third multiplexer connected to said first logic array block in said first set, and a fourth multiplexer connected to said first logic array block in said second set; and a separate RAM bit control input coupled to each of said multiplexers.
Claim 14
Dependent Claim
205 words
A programmable logic device comprising: a plurality of M global conductors; a plurality of logic array blocks, each of which has a plurality of N inputs, a first set of logic array blocks being on a first side of said global conductors, a second set of logic array blocks being on a second side of said global conductors; a plurality of first level multiplexers, each coupled to a set of said global conductors, each of said first level multiplexers having (M*K)/(N*S) global conductor inputs, where S is the number of first level multiplexers in a group, and K is the number ways into a logic array block from a given global conductor; a plurality of second-level multiplexers, each second-level multiplexer having S inputs for coupling to one of said groups of first level multiplexers and an output coupled to one of said logic array block inputs; wherein a single connection connects one of said global conductors to both an input of a first second-level multiplexer connected to a first logic array block in said first set, and an input of a second second-level multiplexer connected to a first logic array block in said second set, wherein said first logic array blocks are opposite each other.
Claim 15
Dependent Claim
205 words
A programmable logic device comprising: a plurality of M global conductors; a plurality of logic array blocks, each of which has a plurality of N inputs, a first set of logic array blocks being on a first side of said global conductors, a second set of logic array blocks being on a second side of said global conductors; a plurality of first level multiplexers, each coupled to a set of said global conductors, each of said first level multiplexers having (M*K)/(N*S) global conductor inputs, where S is the number of first level multiplexers in a group, and K is the number ways into a logic array block from a given global conductor; a plurality of second-level multiplexers, each second-level multiplexer having S inputs for coupling to one of said groups of first level multiplexers and an output coupled to one of said logic array block inputs; wherein a single connection connects one of said global conductors to both an input of a first second-level multiplexer connected to a first logic array block in said first set, and an input of a second second-level multiplexer connected to a first logic array block in said second set, wherein said first logic array blocks are opposite each other.
Claim 16
Dependent Claim
19 words
The programmable logic device of claim 12 wherein S=2, with two first level multiplexers connected to each second-level multiplexer.
Claim 17
Dependent Claim
19 words
The programmable logic device of claim 12 wherein S=4, with four first level multiplexers connected to each second-level multiplexer.
Claim 18
Dependent Claim
19 words
The programmable logic device of claim 14 wherein each of said first level multiplexers is a M/(N*2) input multiplexer.
Claim 19
Dependent Claim
46 words
The programmable logic device of claim 12 wherein said single connection also connects to an input of a third multiplexer connected to said first logic array block in said first set, and a fourth multiplexer connected to said first logic array block in said second set.
Claim 20
Dependent Claim
17 words
The programmable logic device of claim 16 wherein said first and third multiplexers are adjacent each other.
Claim 21
Dependent Claim
17 words
The programmable logic device of claim 12 wherein said device is integrated on a single silicon chip.
Claim 22
Dependent Claim
14 words
A digital system comprising a programmable logic device as set forth in claim 12.
Claim 23
Independent Claim
147 words
A method for programming a programmable logic device comprising: providing a plurality of global conductors; providing a plurality of logic array blocks, each of which has a plurality of inputs and at least one output, a first set of logic array blocks being on a first side of said global conductors, a second set of logic array blocks being on a second side of said global conductors; providing a plurality of multiplexers, each multiplexer having a plurality of inputs for coupling to different ones of said global conductors and an output coupled to one of said logic array block inputs; connecting, with a single connection, one of said global conductors to both an input of a first multiplexer connected to a first logic array block in said first set, and an input of a second multiplexer connected to a first logic array block in said second set.
Claim 24
Independent Claim
147 words
A method for programming a programmable logic device comprising: providing a plurality of global conductors; providing a plurality of logic array blocks, each of which has a plurality of inputs and at least one output, a first set of logic array blocks being on a first side of said global conductors, a second set of logic array blocks being on a second side of said global conductors; providing a plurality of multiplexers, each multiplexer having a plurality of inputs for coupling to different ones of said global conductors and an output coupled to one of said logic array block inputs; connecting, with a single connection, one of said global conductors to both an input of a first multiplexer connected to a first logic array block in said first set, and an input of a second multiplexer connected to a first logic array block in said second set.
Claim 25
Dependent Claim
92 words
The method of claim 20 wherein there are M global conductors, N inputs to each of said first logic array blocks, and wherein said first and second multiplexers are second-level multiplexers, and further comprising the step of providing a plurality of first level multiplexers coupling said global conductors to said first and second second-level multiplexers, each of said first-level multiplexers having (M*K)/(N*S) global conductor inputs, where S is the number of inputs into each second-level multiplexer, and K is the number ways into a logic array block from a given global conductor.
Claim 26
Dependent Claim
16 words
The method of claim 21 wherein S=2, with two first-level multiplexers connected to each second-level multiplexer.
Claim 27
Dependent Claim
16 words
The method of claim 21 wherein S=4, with four first-level multiplexers connected to each second-level multiplexer.
Claim 28
Dependent Claim
17 words
The method of claim 23 wherein each of said first level multiplexers is a M/(N*2) input multiplexer.
Claim 29
Dependent Claim
47 words
The method of claim 20 further comprising the step of connecting said single connection to an input of a third multiplexer connected to said first logic array block in said first set, and a fourth multiplexer connected to said first logic array block in said second set.
Claim 30
Dependent Claim
23 words
The method of claim 20 further comprising the step of programming a plurality of separate RAM bit control inputs coupled to said multiplexers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |