US5941986A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Micro-code sequencer with branch-taken and branch-not-taken micro-code vectors sharing common address to eliminate taken branch penalties
Assignee: Intel Corp
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Filing: 1993-04-30
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Granted: 1999-08-24
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Expires: 2013-04-30
Abstract
Abstract The dual-ported micro-code sequencer includes a micro-code ROM which provides micro-code vectors to a latch for access by a data path logic unit. The latch allows for pipe-lining whereby one micro-code vector may be fetched while a second micro-code vector is being executed by the data path logic unit. Micro-code vectors provided by the ROM may include branched vectors controlled by branch conditions. Two output ports are provide to the micro-code ROM for simultaneously outputting both branch-taken vectors and branch-not-taken vectors to a multiplexer connected to the input of the latch. The multiplexer and the two output ports are provided such that both the branch-taken and the branch-not-taken vectors are available to the latch input. Thus, once the branch condition is evaluated the correct branched vector is latched for access by the data path logic. The dual-ported architecture substantially eliminates a problem in pipelined micro-code sequencers wherein a clock cycle is wasted if a branch is taken. The micro-code ROM is written such that the branch-taken and branch-not-taken vectors share a common micro-code address.
Inventors
- 👤 Upendra M. Kulkarni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/267; G06F9/28
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
221 words
A device for processing micro-code, comprising: micro-code means for providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro code vectors, branch-taken micro-code vectors and corresponding branch-not-taken micro-code vectors, with each branch-taken micro-code vector and corresponding branch-not-taken micro-code vector sharing a common micro-address; output means for outputting micro-code vectors from said micro-code means, with a branch-taken micro-code vector and a corresponding branch-not-taken micro-code vector being output substantially in parallel; micro-code vector selection means, connected to said output means, for selecting between said branch-taken micro-code vector and said corresponding branch-not-taken micro-code vector; micro-code vector address selection means connected to said micro-code means for selecting micro-code vectors to be output from said output means without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selection means comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing address stored in said pointer on each clock cycle such that micro-code vector address selection means selects next sequentially stored micro-code vectors in said micro-code means after selecting branch condition micro-vectors; and data path logic unit coupled to said output means for executing said micro-code vectors, wherein said data path logic unit executes said branch condition vectors a clock cycle after which said branch condition micro-code vectors are retrieved from said micro-code means.
Claim 2
Independent Claim
221 words
A device for processing micro-code, comprising: micro-code means for providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro code vectors, branch-taken micro-code vectors and corresponding branch-not-taken micro-code vectors, with each branch-taken micro-code vector and corresponding branch-not-taken micro-code vector sharing a common micro-address; output means for outputting micro-code vectors from said micro-code means, with a branch-taken micro-code vector and a corresponding branch-not-taken micro-code vector being output substantially in parallel; micro-code vector selection means, connected to said output means, for selecting between said branch-taken micro-code vector and said corresponding branch-not-taken micro-code vector; micro-code vector address selection means connected to said micro-code means for selecting micro-code vectors to be output from said output means without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selection means comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing address stored in said pointer on each clock cycle such that micro-code vector address selection means selects next sequentially stored micro-code vectors in said micro-code means after selecting branch condition micro-vectors; and data path logic unit coupled to said output means for executing said micro-code vectors, wherein said data path logic unit executes said branch condition vectors a clock cycle after which said branch condition micro-code vectors are retrieved from said micro-code means.
Claim 3
Dependent Claim
16 words
The device for processing micro-code of claim 1, wherein said micro-code means comprises a micro-code ROM.
Claim 4
Dependent Claim
23 words
The device for processing micro-code of claim 2, wherein said output means comprises first and second output ports, respectively, of said micro-code ROM.
Claim 5
Dependent Claim
16 words
The device for processing micro-code of claim 1, wherein said micro-vector selection means comprises a multiplexer.
Claim 6
Dependent Claim
24 words
The device for processing micro-code of claim 1, further including micro-code execution means for receiving and executing micro-code vectors selected by said selection means.
Claim 7
Dependent Claim
58 words
The device for processing micro-code of claim 5, wherein said micro-code execution means comprises: a latch connected to said micro-code vector selection means, said latch storing said micro-code vectors selected by said selection means; and a data path logic unit, connected to said latch, said data path logic unit accessing and processing micro-code vectors stored in said latch.
Claim 8
Dependent Claim
278 words
A computer system, comprising: a microprocessor means for processing instructions, a memory means for storing data, input/output means for inputting and outputting data from said microprocessor, and a bus means for interconnecting said microprocessor, said memory and said input/output devices; with said microprocessor means having an instruction decoder means for decoding instructions, a micro-code means for providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro-code vectors, branch-taken micro-code vectors and branch-not-taken micro-code vectors, a micro-code execution means for executing said micro-code vectors, and a micro-code sequencer means for retrieving micro-code vectors from said micro-code means and for providing said micro-code vectors to said data path logic units; wherein said micro-code sequencer means includes first and second output means for outputting micro-code vectors from said micro-code means, said branch-not-taken micro-code vectors being output from said first output means and said branch-taken micro-code vectors being output from said second output means, said branch-taken and branch-not-taken micro-code vectors sharing a common micro-address and being output in parallel; micro-code vector selection means, connected to said micro-code vector output means, for selecting one of said branch-taken micro-code vectors and said branch-not-taken micro-code vectors; and micro-code vector address selection means connected to said micro-code means for selecting micro-code vectors to be output from said output means without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selection means comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selection means selects next sequentially stored micro-code vectors in said micro-code means after selecting branch condition micro-vectors.
Claim 9
Dependent Claim
278 words
A computer system, comprising: a microprocessor means for processing instructions, a memory means for storing data, input/output means for inputting and outputting data from said microprocessor, and a bus means for interconnecting said microprocessor, said memory and said input/output devices; with said microprocessor means having an instruction decoder means for decoding instructions, a micro-code means for providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro-code vectors, branch-taken micro-code vectors and branch-not-taken micro-code vectors, a micro-code execution means for executing said micro-code vectors, and a micro-code sequencer means for retrieving micro-code vectors from said micro-code means and for providing said micro-code vectors to said data path logic units; wherein said micro-code sequencer means includes first and second output means for outputting micro-code vectors from said micro-code means, said branch-not-taken micro-code vectors being output from said first output means and said branch-taken micro-code vectors being output from said second output means, said branch-taken and branch-not-taken micro-code vectors sharing a common micro-address and being output in parallel; micro-code vector selection means, connected to said micro-code vector output means, for selecting one of said branch-taken micro-code vectors and said branch-not-taken micro-code vectors; and micro-code vector address selection means connected to said micro-code means for selecting micro-code vectors to be output from said output means without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selection means comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selection means selects next sequentially stored micro-code vectors in said micro-code means after selecting branch condition micro-vectors.
Claim 10
Dependent Claim
49 words
The device for processing micro-code of claim 1, wherein said branch-taken micro-code vectors comprise a first stream of micro-code vectors for sequential execution if the branch is taken, and said branch-not-taken micro-code vectors comprise a second stream of micro-code vectors for sequential execution if said branch is not taken.
Claim 11
Dependent Claim
54 words
The device for processing micro-code of claim 8, wherein an initial micro-code vector of said first stream shares a common micro-address with an initial micro-code vector in said second stream and wherein each succeeding micro-code vector in said first stream shares a common micro-address with a succeeding corresponding micro-code vector in said second stream.
Claim 12
Dependent Claim
21 words
The device for processing micro-code of claim 8, wherein said first and second streams each include only a single micro-code vector.
Claim 13
Dependent Claim
32 words
The device for processing micro-code of claim 8, wherein said selection means examines a least significant bit of each selected micro-code vector to identify the last micro-code vector in the micro-code stream.
Claim 14
Independent Claim
206 words
A device for processing micro-code, comprising: micro-code ROM for providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro code vectors, branch-taken micro-code vectors and corresponding branch-not-taken micro-code vectors, with each branch-taken micro-code vector and corresponding branch-not-taken micro-code vector sharing a common micro-address; first and second output ports, connected to said micro-code ROM, for outputting micro-code vectors from said micro-code ROM, said branch-not-taken micro-code vectors being output from said first output port and said branch-taken micro-code vectors being output from said second output port, said branch-taken and branch-not-taken micro-code vectors being output substantially in parallel; a multiplexer, connected to said micro-code vector output ports for selecting between a branch-taken micro-code vector and a corresponding branch-not-taken micro-code vector; and micro-code vector address selector connected to said micro-code ROM for selecting micro-code vectors to be output from said first and second output ports without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selector comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selector selects next sequentially stored micro-code vectors in said micro-code ROM after selecting branch condition micro-vectors.
Claim 15
Independent Claim
206 words
A device for processing micro-code, comprising: micro-code ROM for providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro code vectors, branch-taken micro-code vectors and corresponding branch-not-taken micro-code vectors, with each branch-taken micro-code vector and corresponding branch-not-taken micro-code vector sharing a common micro-address; first and second output ports, connected to said micro-code ROM, for outputting micro-code vectors from said micro-code ROM, said branch-not-taken micro-code vectors being output from said first output port and said branch-taken micro-code vectors being output from said second output port, said branch-taken and branch-not-taken micro-code vectors being output substantially in parallel; a multiplexer, connected to said micro-code vector output ports for selecting between a branch-taken micro-code vector and a corresponding branch-not-taken micro-code vector; and micro-code vector address selector connected to said micro-code ROM for selecting micro-code vectors to be output from said first and second output ports without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selector comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selector selects next sequentially stored micro-code vectors in said micro-code ROM after selecting branch condition micro-vectors.
Claim 16
Dependent Claim
43 words
The device for processing micro-code vectors of claim 12, further including a latch connected to said multiplexer for storing said selected micro-code vector; and a data path logic unit, connected to said latch, for accessing and processing micro-code vectors stored in said latch.
Claim 17
Dependent Claim
260 words
A computer system, comprising: a microprocessor, a memory, input/output devices, and a bus interconnecting said microprocessor, said memory and said input/output devices; with said microprocessor having an instruction decoder, a micro-code ROM, said micro-code ROM providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro-code vectors, branch-taken micro-code vectors and branch-not-taken micro-code vectors, a data path logic unit, and a micro-code sequencer for retrieving micro-code vectors from said micro-code ROM and for providing said micro-code vectors to said data path logic unit; wherein said micro-code sequencer includes first and second output ports, connected to said micro-code ROM, said first and second output ports outputting micro-code vectors from said micro-code ROM, said branch-not-taken micro-code vectors being output from said first output port and said branch-taken micro-code vectors being output from said second output port, said branch-taken and branch-not-taken micro-code vectors sharing a common address and being output in parallel; a multiplexer, connected to said micro-code vector output ports, said multiplexer selecting one of said branch-taken micro-code vectors and said branch-not-taken micro-code vectors; and micro-code vector address selector connected to said micro-code ROM for selecting micro-code vectors to be output from said first and second output ports without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selector comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selector selects next sequentially stored micro-code vectors in said micro-code ROM after selecting branch condition micro-vectors.
Claim 18
Dependent Claim
260 words
A computer system, comprising: a microprocessor, a memory, input/output devices, and a bus interconnecting said microprocessor, said memory and said input/output devices; with said microprocessor having an instruction decoder, a micro-code ROM, said micro-code ROM providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro-code vectors, branch-taken micro-code vectors and branch-not-taken micro-code vectors, a data path logic unit, and a micro-code sequencer for retrieving micro-code vectors from said micro-code ROM and for providing said micro-code vectors to said data path logic unit; wherein said micro-code sequencer includes first and second output ports, connected to said micro-code ROM, said first and second output ports outputting micro-code vectors from said micro-code ROM, said branch-not-taken micro-code vectors being output from said first output port and said branch-taken micro-code vectors being output from said second output port, said branch-taken and branch-not-taken micro-code vectors sharing a common address and being output in parallel; a multiplexer, connected to said micro-code vector output ports, said multiplexer selecting one of said branch-taken micro-code vectors and said branch-not-taken micro-code vectors; and micro-code vector address selector connected to said micro-code ROM for selecting micro-code vectors to be output from said first and second output ports without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selector comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selector selects next sequentially stored micro-code vectors in said micro-code ROM after selecting branch condition micro-vectors.
Claim 19
Dependent Claim
49 words
The device for processing micro-code of claim 12, wherein said branch-taken micro-code vectors comprise a first stream of micro-code vectors for sequential execution if the branch is taken, and said branch-not-taken micro-code vectors comprise a second stream of micro-code vectors for sequential execution if said branch is not taken.
Claim 20
Dependent Claim
54 words
The device for processing micro-code of claim 15, wherein an initial micro-code vector of said first stream shares a common micro-address with an initial micro-code vector in said second stream and wherein each succeeding micro-code vector in said first stream shares a common micro-address with a succeeding corresponding micro-code vector in said second stream.
Claim 21
Dependent Claim
21 words
The device for processing micro-code of claim 15, wherein said first and second streams each include only a single micro-code vector.
Claim 22
Dependent Claim
31 words
The device for processing micro-code of claim 8, wherein said multiplexer examines a least significant bit of each selected micro-code vector to identify the last micro-code vector in the micro-code stream.
Claim 23
Dependent Claim
214 words
In a device for processing micro-code having a micro-code ROM generating micro-code vectors, including branch condition micro-vectors, branch-taken micro-code vectors and branch-not-taken micro-code vectors, a latch for receiving said micro-code vectors, and data path logic for retrieving said micro-code vectors from said latch and performing operations in response thereto, an improvement comprising: providing said micro-code ROM with first and second output ports, said micro-code ROM simultaneously outputting a branch-taken micro-code vector and a branch-not-taken micro-code vector through said first and second output ports, respectively, with said branch-taken micro-code vector and said branch-not-taken micro-code vector sharing a common micro-address; providing a multiplexer, connected between said micro-code ROM and said latch, for selecting between a micro-code vector received from either said first output port or said second output port; and providing a micro-code vector address selector connected to said micro-code ROM for selecting micro-code vectors to be output from said first and second output ports without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selector comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selector selects next sequentially stored micro-code vectors in said micro-code ROM after selecting branch condition micro-vectors.
Claim 24
Dependent Claim
214 words
In a device for processing micro-code having a micro-code ROM generating micro-code vectors, including branch condition micro-vectors, branch-taken micro-code vectors and branch-not-taken micro-code vectors, a latch for receiving said micro-code vectors, and data path logic for retrieving said micro-code vectors from said latch and performing operations in response thereto, an improvement comprising: providing said micro-code ROM with first and second output ports, said micro-code ROM simultaneously outputting a branch-taken micro-code vector and a branch-not-taken micro-code vector through said first and second output ports, respectively, with said branch-taken micro-code vector and said branch-not-taken micro-code vector sharing a common micro-address; providing a multiplexer, connected between said micro-code ROM and said latch, for selecting between a micro-code vector received from either said first output port or said second output port; and providing a micro-code vector address selector connected to said micro-code ROM for selecting micro-code vectors to be output from said first and second output ports without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selector comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selector selects next sequentially stored micro-code vectors in said micro-code ROM after selecting branch condition micro-vectors.
Claim 25
Independent Claim
149 words
A method for processing micro code, comprising: storing sequences of micro-code vectors in a memory device, said sequences of micro-code vectors including branch condition micro-code vectors, branch-taken micro-code vectors and branch-not-taken micro-code vectors with said branch-taken micro-code vectors sharing a common micro-address with corresponding branch-not-taken micro-code vectors; evaluating said branch condition micro-code vectors to determine which of said branch-taken and branch-not-taken micro-code vectors is to be executed; selecting a branch target address containing both branch-taken micro-code vectors and branch-not-taken micro-code vectors in said memory device without retrieving stored addresses in said branch condition micro-code vectors wherein said selecting is performed by retrieving said vectors stored in address locations immediately succeeding said branch condition micro-code vectors; outputting said branch-taken micro-code vectors and said branch-not-taken micro-code vectors in parallel from said memory device; and selecting one of said branch-taken micro-code vectors and said branch-not-taken micro-code vectors, in response to said evaluation.
Claim 26
Independent Claim
149 words
A method for processing micro code, comprising: storing sequences of micro-code vectors in a memory device, said sequences of micro-code vectors including branch condition micro-code vectors, branch-taken micro-code vectors and branch-not-taken micro-code vectors with said branch-taken micro-code vectors sharing a common micro-address with corresponding branch-not-taken micro-code vectors; evaluating said branch condition micro-code vectors to determine which of said branch-taken and branch-not-taken micro-code vectors is to be executed; selecting a branch target address containing both branch-taken micro-code vectors and branch-not-taken micro-code vectors in said memory device without retrieving stored addresses in said branch condition micro-code vectors wherein said selecting is performed by retrieving said vectors stored in address locations immediately succeeding said branch condition micro-code vectors; outputting said branch-taken micro-code vectors and said branch-not-taken micro-code vectors in parallel from said memory device; and selecting one of said branch-taken micro-code vectors and said branch-not-taken micro-code vectors, in response to said evaluation.
Claim 27
Independent Claim
226 words
A device for processing micro-code, comprising: micro-code ROM for providing micro-code vectors, said micro-code vectors including branch condition micro-code vectors identifying branch-taken micro-code vectors and branch-not-taken micro-code vectors, said branch-taken micro-code vectors and said branch-not-taken micro-code vectors sharing a common micro-address said branch-taken micro-code vectors being output through a first output port, said branch-not-taken micro-code vectors being output through a second output port; a latch, connected to said first and second output ports, for storing one of said micro-code vectors, said latch storing said branch-taken micro-code vector if said branch is taken and storing said branch-not-taken micro-code vector otherwise; a data path logic unit, connected to said latch, for retrieving and processing micro-code vectors from said latch; a micro-instruction pointer for holding a current micro-code address and for transmitting said current micro-code address to said micro-code ROM; an adder, connected to said micro-instruction pointer, for incrementing the current micro-code address; and a branch condition multiplexer for receiving branch conditions from said data path logic unit and branch target addresses from said latch and for receiving an incremented current micro-code address from said adder, said branch condition multiplexer transmitting a new micro-code address to said micro-instruction pointer, said new micro-code address replacing said current micro-code address in said micro-instruction pointer, said multiplexer transmitting either an incremented address or a branched address in response to said branch conditions.
Claim 28
Independent Claim
226 words
A device for processing micro-code, comprising: micro-code ROM for providing micro-code vectors, said micro-code vectors including branch condition micro-code vectors identifying branch-taken micro-code vectors and branch-not-taken micro-code vectors, said branch-taken micro-code vectors and said branch-not-taken micro-code vectors sharing a common micro-address said branch-taken micro-code vectors being output through a first output port, said branch-not-taken micro-code vectors being output through a second output port; a latch, connected to said first and second output ports, for storing one of said micro-code vectors, said latch storing said branch-taken micro-code vector if said branch is taken and storing said branch-not-taken micro-code vector otherwise; a data path logic unit, connected to said latch, for retrieving and processing micro-code vectors from said latch; a micro-instruction pointer for holding a current micro-code address and for transmitting said current micro-code address to said micro-code ROM; an adder, connected to said micro-instruction pointer, for incrementing the current micro-code address; and a branch condition multiplexer for receiving branch conditions from said data path logic unit and branch target addresses from said latch and for receiving an incremented current micro-code address from said adder, said branch condition multiplexer transmitting a new micro-code address to said micro-instruction pointer, said new micro-code address replacing said current micro-code address in said micro-instruction pointer, said multiplexer transmitting either an incremented address or a branched address in response to said branch conditions.
Claim 29
Independent Claim
208 words
A device for processing micro-code, comprising: micro-code means for providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro-code vectors triggering one of a plurality of alternative streams of micro-code vectors, with each micro-code vector of one of said alternative streams of micro-code vectors sharing a common micro-address with a corresponding micro-code vector of another of said alternative streams; a plurality of output means for outputting micro-code vectors from said micro-code means, with one of said alternative streams of micro-code vectors being output along each of said plurality of output means, said alternative streams of micro-code vectors being output in parallel; micro-code vector selection means, connected to said output means, for selecting one of said streams of micro-code vectors; and micro-code vector address selection means connected to said micro-code means for selecting micro-code vectors to be output from said output means without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selection means comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selection means selects next sequentially stored micro-code vectors in said micro-code means after selecting branch condition micro-vectors.
Claim 30
Independent Claim
208 words
A device for processing micro-code, comprising: micro-code means for providing sequences of micro-code vectors, said sequences of micro-code vectors including branch condition micro-code vectors triggering one of a plurality of alternative streams of micro-code vectors, with each micro-code vector of one of said alternative streams of micro-code vectors sharing a common micro-address with a corresponding micro-code vector of another of said alternative streams; a plurality of output means for outputting micro-code vectors from said micro-code means, with one of said alternative streams of micro-code vectors being output along each of said plurality of output means, said alternative streams of micro-code vectors being output in parallel; micro-code vector selection means, connected to said output means, for selecting one of said streams of micro-code vectors; and micro-code vector address selection means connected to said micro-code means for selecting micro-code vectors to be output from said output means without retrieving stored addresses in said branch condition micro-vectors, said micro-code vector address selection means comprising a pointer for identifying said micro-vectors to be output and a plus one adder for incrementing addresses stored in said pointer on each clock cycle such that micro-code vector address selection means selects next sequentially stored micro-code vectors in said micro-code means after selecting branch condition micro-vectors.
Claim 31
Dependent Claim
52 words
The micro-code processing device of claim 22, further including micro-code execution means for executing micro-code vectors selected by said selection means, for evaluating said branch condition micro-code vectors to determine which of said alternative streams is to be selected, and for transmitting a signal representative of said evaluation to said selection means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |