US4812970A
Expired / Lapsed
US
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Microprogram control system
Assignee: Fujitsu Ltd
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Filing: 1984-11-08
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Granted: 1989-03-14
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Expires: 2004-11-08
Abstract
Abstract According to the present invention, in a data processing unit which executes pipeline processings by developing an instruction into multiple flows through microprogram control, is a method provided where the microinstruction is divided into a part for controlling a first stage of pipeline and a part for controlling second and successive stages. The part for controlling the first stage is read simultaneously with the part for controlling the second and successive stages of the flow prior to the current flow. The present invention thus provides an advantage in that microprogram control can be employed for the first stage of the pipeline and resulting in a data processing unit which is capable of executing more flexible pipeline processings than the prior art can be formed. In an instructs a field for controlling the first stage of pipeline is separated from the fields for controlling the other stages and it is read at the same timing as that for reading the fields for controlling the second and successive stages of the flow just prior to the current flow. As a result, the first state of pipeline in the second and successive flow is controlled by microprogram control.
Inventors
- 👤 Toshiaki Kitamura
- 👤 Katsumi Onishi
- 👤 Yuji Oinaga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/22; G06F9/28
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
144 words
A microprogram control method for a multi-flow machine instruction executed by several microinstructions, each microinstruction having plural parts, using a pipeline having a plurality of execution stages each microinstruction part controlling a different stage, and each flow controlled by a different microinstruction, said method comprising the steps of: hardware decoding the machine instruction for controlling a first stage of a first flow in said pipeline, fetching a second part of a first microinstruction for controlling second and successive stages in the first flow and fetching a first part of a second microinstruction for controlling a first stage in a second flow, respectively in parallel; and executing the second part of the first microinstruction, executing the first part of the second microinstruction and fetching a second part of the second microinstruction for controlling the second and successive stages of the second flow, respectively in parallel.
Claim 2
Dependent Claim
144 words
A microprogram control method for a multi-flow machine instruction executed by several microinstructions, each microinstruction having plural parts, using a pipeline having a plurality of execution stages each microinstruction part controlling a different stage, and each flow controlled by a different microinstruction, said method comprising the steps of: hardware decoding the machine instruction for controlling a first stage of a first flow in said pipeline, fetching a second part of a first microinstruction for controlling second and successive stages in the first flow and fetching a first part of a second microinstruction for controlling a first stage in a second flow, respectively in parallel; and executing the second part of the first microinstruction, executing the first part of the second microinstruction and fetching a second part of the second microinstruction for controlling the second and successive stages of the second flow, respectively in parallel.
Claim 3
Dependent Claim
75 words
A microprogram control method according to claim 1, further comprising: using a first memory for storing said first part of said second microinstruction and a second memory for storing said second part of said first and second microinstructions; delaying address information for accessing said first memory by at least one stage and accessing said second memory in said second flow; and accessing said first memory and said second memory in parallel in the second flow.
Claim 4
Dependent Claim
60 words
A microprogram control method according to claim 2, further including: using the second memory including a first flow memory which stores microinstructions for processing of the first flow and a second flow memory which stores microinstructions for processing of the second and successive flows; and using microinstructions stored in the first and second flow memories with a different bit width.
Claim 5
Dependent Claim
34 words
A microprogram control method according to claim 1, wherein the processing which controls the first stage corresponding to the first flow among the processings developed in said multiple flows is executed using hardware control.
Claim 6
Independent Claim
184 words
A method of processing a multi-flow machine instruction, having first and second flows where execution of each flow is controlled by a different microinstruction, in a pipeline processing unit having a hardware decoder, a microprogram controlled control storage access stage and microprogram controlled successive stages, each microinstruction having plural parts each part controlling one of the stages, the microinstructions being shifted through the successive stages, said method comprising the steps of: (a) decoding the machine instruction for the first stage of the first flow using the hardware decoder; (b) first fetching and second using a first flow microinstruction for controlling the microprogram controlled successive stages of the first flow and simultaneously, with said first fetching, fetching a decode control storage access stage microinstruction for the second flow; and (c) executing the access stage microinstruction of the second flow using the microprogram controlled control storage access stage and simultaneously, with the executing, fetching a second flow microinstruction for controlling the microprogram controlled successive stages of the second flow and then executing the fetched second flow microinstruction for controlling the successive stages of the second flow.
Claim 7
Independent Claim
184 words
A method of processing a multi-flow machine instruction, having first and second flows where execution of each flow is controlled by a different microinstruction, in a pipeline processing unit having a hardware decoder, a microprogram controlled control storage access stage and microprogram controlled successive stages, each microinstruction having plural parts each part controlling one of the stages, the microinstructions being shifted through the successive stages, said method comprising the steps of: (a) decoding the machine instruction for the first stage of the first flow using the hardware decoder; (b) first fetching and second using a first flow microinstruction for controlling the microprogram controlled successive stages of the first flow and simultaneously, with said first fetching, fetching a decode control storage access stage microinstruction for the second flow; and (c) executing the access stage microinstruction of the second flow using the microprogram controlled control storage access stage and simultaneously, with the executing, fetching a second flow microinstruction for controlling the microprogram controlled successive stages of the second flow and then executing the fetched second flow microinstruction for controlling the successive stages of the second flow.
Claim 8
Dependent Claim
152 words
A pipeline processing unit control system having a decoding stage and successive stages, said system comprising: an instruction register for storing a multi-flow machine instruction having first and second flows where execution of each flow is controlled by a different microinstruction and each microinstruction having plural parts each part controlling one of the stages; a hardware decoder, connected to said instruction register, for decoding the multi-flow machine instruction for the first flow in the decoding stage; a first microprogram memory, connected to said instruction register, for storing microinstructions for the successive stages of the first and second flows; a second microprogram memory, connected to said instruction register, for storing microinstructions for a control storage access stage of the second flow; and microprogram decoder means, connected to said first and second microprogram memories, for decoding the microinstructions in the access stage of the second flow and in successive stages in the second flow.
Claim 9
Dependent Claim
152 words
A pipeline processing unit control system having a decoding stage and successive stages, said system comprising: an instruction register for storing a multi-flow machine instruction having first and second flows where execution of each flow is controlled by a different microinstruction and each microinstruction having plural parts each part controlling one of the stages; a hardware decoder, connected to said instruction register, for decoding the multi-flow machine instruction for the first flow in the decoding stage; a first microprogram memory, connected to said instruction register, for storing microinstructions for the successive stages of the first and second flows; a second microprogram memory, connected to said instruction register, for storing microinstructions for a control storage access stage of the second flow; and microprogram decoder means, connected to said first and second microprogram memories, for decoding the microinstructions in the access stage of the second flow and in successive stages in the second flow.
Claim 10
Dependent Claim
62 words
A system as recited in claim 6, further comprising: a latch, connected between said instruction register and said first microprogram memory, for storing an address of the microinstructions in the successive stages of the first and second flows; and an address generating circuit, connected to said decoder means and said latch, for generating an address for the microinstructions of the second flow.
Claim 11
Dependent Claim
152 words
A pipeline processing unit control system having a decoding stage and successive stages, said system comprising: an instruction register for storing a multi-flow instruction having first and second flows where execution of each flow is controlled by a different microinstruction, each microinstruction having plural parts each part controlling one of the stages; a hardware decoder, connected to said instruction lregister, for decoding the multi-flow machine instruction for the first flow in the decoding stage; a first microprogram memory, connected to said instruction register, for storing microinstructions for the successive stages of the first flow; a second microprogram memory, connected to said instruction register, for storing microinstructions for a control store access stage of the second flow; a third microprogram memory, connected to said instruction register, for storing microinstructions for the successive stages of the second flow; and microprogram decoder means, connected to said first through third microprogram memories, for decoding the microinstructions.
Claim 12
Dependent Claim
152 words
A pipeline processing unit control system having a decoding stage and successive stages, said system comprising: an instruction register for storing a multi-flow instruction having first and second flows where execution of each flow is controlled by a different microinstruction, each microinstruction having plural parts each part controlling one of the stages; a hardware decoder, connected to said instruction lregister, for decoding the multi-flow machine instruction for the first flow in the decoding stage; a first microprogram memory, connected to said instruction register, for storing microinstructions for the successive stages of the first flow; a second microprogram memory, connected to said instruction register, for storing microinstructions for a control store access stage of the second flow; a third microprogram memory, connected to said instruction register, for storing microinstructions for the successive stages of the second flow; and microprogram decoder means, connected to said first through third microprogram memories, for decoding the microinstructions.
Claim 13
Dependent Claim
73 words
A system as recited in claim 8, further comprising: a selector connected to said instruction register and said second microprogram memory; a latch, connected between said selector and said third microprogram memory, for storing an address of the microinstructions in the successive stages of the first and second flows; and an address generating circuit, connected to said decoder means and said selector, for generating an address for the microinstructions of the second flow.
Claim 14
Dependent Claim
42 words
A method according to claim 1, wherein said pipeline includes microinstruction stage registers corresponding to the pipeline stages and said method includes shifting the microinstructions through the stage registers and controlling the corresponding pipeline stage using outputs of the corresponding stage register.
Claim 15
Dependent Claim
41 words
A method according to claim 5, wherein said pipeline includes microinstruction stage registers corresponding to pipeline stages and said method includes shifting the microinstructions through the stage registers and controlling the corresponding pipeline stage using outputs of the corresponding stage register.
Claim 16
Dependent Claim
58 words
A control system according to claim 6, the pipeline having pipeline execution stages and said control system further comprising series connected microinstruction stage registers corresponding to the pipeline execution stages and connected to said first program memory, each register corresponding to a stage, the microinstructions being shifted successively through said stage registers during the first and second flows.
Claim 17
Dependent Claim
58 words
A control system according to claim 8, the pipeline having pipeline execution stages and said control system further comprising series connected microinstruction stage registers corresponding to the pipeline execution stages, and connected to said first program memory, each register corresponding to a stage, the microinstructions being shifted successively through said stage registers during the first and second flows.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |