Computer and method for executing target instructions

Claim 2

A digital computer comprising, a microstore for storing subroutines of microinstructions, said microinstructions accessable, when addressed by microaddress, for controlling said digital computer, microaddress generation means for generating microaddresses for addressing said microstore to access microinstructions, said microaddress generation means including a link memory having locations for storing predetermined microaddresses for linking subroutines of microinstructions, including a stack memory having locations for storing microaddresses in connection with the execution of microinstructions, and including generation control means for controlling the accessing of microaddresses from said said link memory and said stack memory to address said microstore wherein said generation control means includes stack pointer means storing a stack pointer for pointing to locations in said stack memory and to an empty location; includes pointer means for storing a link pointer pointing to locations in said link memory, said link pointer means including link counter means for storing said link pointer as a number and controlled to be counted each time a microaddress is accessed from said link memory, includes means for controlling the locations pointed to by said stack pointer means and said link pointer means, and includes selection means for selecting microaddresses from locations pointed to by said link pointer only when said stack pointer points to said empty location.

Claim 3

The computer of claim 1 wherein said stack pointer means includes stack counter means for storing said stack pointer as a number and controlled to count away from a number representing said empty location for each microaddress loaded into said stack memory and controlled to count toward the number representing said empty location for each microaddress accessed from said stack memory.

Claim 4

The computer of claim 2 wherein said stack counter means includes first and second stack counters connected to be stepped in parallel, said stack pointer means including means for presetting said stack counters to different numbers, said stack pointer means including multiplexer means for selecting the stack pointer as a number from one or the other of said first or second stack counters as a function of whether microaddresses are being stored into said stack memory or are being fetched from said stack memory.

Claim 5

The computer of claim 1 wherein said link counter means includes first and second link counters connected to be stepped in parallel, said link pointer means including means for presetting said link counters to different numbers, said link pointer means including multiplexer means for selecting the link pointer as a number from one or the other of said first or second link counters to sequentially access microaddresses from said link memory.

Claim 6

The computer of claim 4 including link pointer enabling means for enabling said first and second link counters to be stepped only when said stack pointer is pointing to the empty location.

Claim 7

The computer of claim 3 including means for establishing first and second types of operation to pop microaddresses from and push microaddresses into said microaddress generation means, respectively, including enabling means for enabling said stack counters to be counted away from the number representing said empty location in response to a second type of operation and for enabling said stack counters to be counted toward said empty location whenever a first type of operation fetches a microaddress from said stack memory, said stack pointer means including means for disabling said stack counters in the absence of a first or second type of operation .

Claim 8

The computer of claim 1 wherein said microaddress generation means includes one or more additional microaddress source units for providing microaddresses and wherein said generation control means includes means for controlling the accessing of microaddresses from said one or more additional microaddress source units.

Claim 9

The computer of claim 7 wherein one of said additional microaddress source units is a next sequential unit including a next sequential register and including adder means for adding one to the current microaddress to form a next sequential microaddress for storage in said next sequential register.

Claim 10

The computer of claim 7 wherein one of said additional microaddress source units is an implicit register and means for storing microaddresses into said implicit register directly from a field contained in microinstructions accessed from said microstore.

Claim 11

The computer of claim 7 wherein one of said additional microaddress source units is an external unit including an external register, including an external microaddress counter where said external register is loadable with the contents of said external microaddress counter, and including means for controlling said external microaddress counter to be preloaded and stepped under control of said computer.

Claim 12

The computer of claim 7 wherein one of said additional microaddress source units is an indirect register loadable under control of microinstructions accessed from said microstore.

Claim 13

The computer of claim 1 wherein said microaddress generation means includes a top-of-stack register and includes stack multiplexer control means for selecting microaddresses from said stack memory and said link memory for loading said top of stack register.

Claim 14

A digital computer comprising, means for providing target instructions each having a unique op code a microstore for storing subroutines of microinstructions, said microinstructions accessable, when addressed by microaddresses, for controlling said digital computer in the execution of target instructions, microaddress generation means for generating microaddresses for addressing said microstore to access microinstructions, said microaddress generation means including a link memory having a different plurality of locations associated with each one of a number of target instructions where said locations store predetermined microaddresses for linking subroutines of microinstructions unique to each target instruction, including link pointer means for storing a link number pointing to a selected one of said plurlaity of locations where said link pointer means includes means for changing the link number each time a microaddress is accessed from said link memory, including means for using the op code from each target instruction with said link number to address each of said plurality of locations for each of said target instructions to obtain subroutines of microinstructions for executing each target instruction, and including generation control means for controlling the accessing of microaddresses from said link memory to address said microstore.

Claim 15

A digital computer comprising, means for providing target instructions each having a unique op code a microstore for storing subroutines of microinstructions, said microinstructions accessable, when addressed by microaddresses, for controlling said digital computer in the execution of target instructions, microaddress generation means for generating microaddresses for addressing said microstore to access microinstructions, said microaddress generation means including a link memory having a different plurality of locations associated with each one of a number of target instructions where said locations store predetermined microaddresses for linking subroutines of microinstructions unique to each target instruction, including link pointer means for storing a link number pointing to a selected one of said plurlaity of locations where said link pointer means includes means for changing the link number each time a microaddress is accessed from said link memory, including means for using the op code from each target instruction with said link number to address each of said plurality of locations for each of said target instructions to obtain subroutines of microinstructions for executing each target instruction, and including generation control means for controlling the accessing of microaddresses from said link memory to address said microstore.

Claim 16

The digital computer of claim 13 wherein said microaddress generation means includes a stack memory having locations for storing microaddresses in connection with the execution of microinstructions and wherein said generation control means includes means for controlling the accessing of microaddresses from said stack memory.

Claim 17

The computer of claim 14 wherein said generation control means includes stack pointer means storing a stack pointer for pointing to locations in said stack memory and to an empty location; includes means for controlling the location pointed to by said stack pointer means and includes selection means for selecting microaddresses from locations pointed to by said link pointer only when said stack pointer points said empty location.

Claim 18

The computer of claim 15 wherein said stack pointer means includes stack counter means for storing said stack pointer as a number and controlled to count away from a number representing said empty location for each microaddress loaded into said stack memory and controlled to count toward the number representing said empty location for each microaddress accessed from said stack memory.

Claim 19

The computer of claim 16 wherein said stack counter means includes first and second stack counters connected to be stepped in parallel, said stack pointer means including means for presetting said stack counters to different numbers, said stack pointer means including multiplexer means for selecting the stack pointer as a number from one or the other of said first or second stack counters as a function of whether microaddresses are being stored into said stack memory or are being fetched from said stack memory.

Claim 20

The computer of claim 13 wherein said link pointer means includes means for incrementing said link number each time a microaddress is accessed from said link memory.

Claim 21

The computer of claim 18 wherein said link counter means includes first and second link counters connected to be stepped in parallel, said link pointer means including means for presetting said link counters to different numbers, said link pointer means including multiplexer means for selecting the link pointer as a number from one or the other of said first or second link counters to form link memory addresses in combination with said op code to sequentially access microaddresses from said link memory.

Claim 22

The computer of claim 19 including link pointer enabling means for enabling said first and second link counters to be stepped only when said stack pointer is pointing to the empty location.

Claim 23

The computer of claim 17 including means for establishing first and second types of operation to pop microaddresses from and push microaddresses into said microaddress generation means, respectively, including enabling means for enabling said stack counters to be counted away from the number representing said empty location in response to a second type of operation and for enabling said stack counters to be counted toward said empty location whenever a first type of operation fetches a microaddress from said stack memory, said stack pointer means including means for disabling said stack counters in the absence of a first or second type of operation.

Claim 24

The computer of claim 13 wherein said microaddress generation means includes one or more additional microaddress source units for providing microaddresses and wherein said generation control means includes means for controlling the accessing of microaddresses from said one or more additional microaddress source units.

Claim 25

The computer of claim 22 wherein one of said additional microaddress source units is an implicit register and means for storing microaddresses into said implicit register directly from a field contained in microinstructions accessed from said microstore.

Claim 26

The computer of claim 13 wherein said microaddress generation means includes a top-of-stack register and includes stack multiplexer control means for selecting microaddresses from said stack memory and said link memory for loading said top of stack register.

Claim 27

A digital computer for executing target instructions comprising, a microstore for storing microinstructions, said microinstructions accessable from said microstore, when addressed by microaddresses, for controlling said digital computer, means responsive to microinstructions accessed from said microstore for performing data manipulations under control of said microinstructions, microaddress generation means for sequentially generating microaddresses for addressing said microstore to access sequentially microinstructions from said microstore, said microaddress generation means comprising, a stack unit including a link memory for storing groups of predetermined microaddresses each of said groups of predetermined microaddresses specifying a corresponding predetermined group of microinstructions to be linked and sequentially executed for each target instruction, each of said predetermined microaddresses in a group located in sequential locations, including a stack memory for storing and fetching microaddresses during the execution of said predetermined group of microinstructions, including a top-of-stack register for storing a microaddress from said stack memory or said link memory, and including stack control means for controlling the selection of microaddresses for said top-of-stack register independent of the execution of microinstructions, an additional microaddress source unit, generation control means for controlling the accessing of microaddresses from said stack unit and from said additional microaddress source unit.

Claim 28

A digital computer for executing target instructions comprising, a microstore for storing microinstructions, said microinstructions accessable from said microstore, when addressed by microaddresses, for controlling said digital computer, means responsive to microinstructions accessed from said microstore for performing data manipulations under control of said microinstructions, microaddress generation means for sequentially generating microaddresses for addressing said microstore to access sequentially microinstructions from said microstore, said microaddress generation means comprising, a stack unit including a link memory for storing groups of predetermined microaddresses each of said groups of predetermined microaddresses specifying a corresponding predetermined group of microinstructions to be linked and sequentially executed for each target instruction, each of said predetermined microaddresses in a group located in sequential locations, including a stack memory for storing and fetching microaddresses during the execution of said predetermined group of microinstructions, including a top-of-stack register for storing a microaddress from said stack memory or said link memory, and including stack control means for controlling the selection of microaddresses for said top-of-stack register independent of the execution of microinstructions, an additional microaddress source unit, generation control means for controlling the accessing of microaddresses from said stack unit and from said additional microaddress source unit.

Claim 29

The computer of claim 25 including means for providing target instructions each having an op code and wherein said stack unit includes address means for addressing said link memory with op codes from each target instruction, one or more of said op codes specifying a plurality of said predetermined microaddresses in a group whereby subroutines of microinstructions for executing each target instruction are accessed uniquely for each target instruction.

Claim 30

The computer of claim 26 wherein said generation control means includes stack pointer means storing a stack pointer for pointing to locations in said stack memory and to an empty location; includes link pointer means for storing a link pointer pointing in combination with said op code to a predetermined number of locations in said link memory for each target instruction where said predetermined number of locations store said predetermined microaddresses in a group, includes means for controlling the locations pointed to by said stack pointer means and said link pointer means, and includes selection means for selecting microaddresses from locations pointed to by said link pointer only when said stack pointer points to said empty location.

Claim 31

The computer of claim 27 wherein said stack pointer means includes stack counter means for storing said stack pointer as a number and means for controlling said stack counter means to count away from a number representing said empty location for each microaddress loaded into said stack memory and to count toward the number representing said empty location for each microaddress accessed from said stack memory.

Claim 32

The computer of claim 28 wherein said stack counter means includes first and second stack counters connected to be stepped in parallel, said stack pointer means including means for presetting said stack counters to different numbers said stack pointer means including multiplexer means for selecting the stack pointer as a number from one or the other of said first or second stack counters as a function of whether microaddresses are being stored into said stack memory or are being fetched from said stack memory.

Claim 33

The computer of claim 27 wherein said link pointer means includes link counter means for storing said link pointer as a number from a number range equal to said predetermined number and wherein said link counter means is controlled to be counted each time a microaddress is accessed from said link memory.

Claim 34

The computer of claim 30 further including a stack source unit forming an additional source of microaddresses and including means for accessing microaddresses from said stack source unit after said predetermined number of microaddresses have been accessed from said link memory.

Claim 35

The computer of claim 31 wherein said stack source unit includes implicit address means connected to provide microaddresses directly from a field within a microinstruction.

Claim 36

The computer of claim 30 wherein said predetermined number is four.

Claim 37

The computer of claim 30 wherein said link counter means includes first and second link counters connected to be stepped in parallel over said number range, said link pointer mens including means for presetting said link counters to different numbers differing by one count for each new one of said target instructions, said link pointer means including multiplexer means for selecting the link pointer as a number from one or the other of said first or second link counters to form link memory addresses in combination with said op code to sequentially access a number, up to said predetermined number, of microaddresses from said link memory.

Claim 38

The computer of claim 34 including link pointer enabling means for enabling said first and second link counters to be stepped only when said stack pointer is pointing to the empty location.

Claim 39

The computer of claim 35 including means for establishing first and second types of operation to pop microaddresses from and push microaddresses into said microaddress generation means, respectively, including enabling means for enabling said stack counters to be counted away from the number representing said empty location in response to a second type of operation and for enabling said stack counters to be counted toward said empty location whenever a first type of operation fetches a microaddress from said stack memory, said stack pointer means including means for disabling said stack counters in the absence of a first or second type of operation.

Claim 40

The computer of claim 25 wherein said microaddress generation means includes one or more additional microaddress source units for providing microaddresses and wherein said generation control means includes means for controlling the accessing of microaddresses from said one or more additional microaddress source units.

Claim 41

The computer of claim 37 wherein one of said additional microaddress source units is an implicit register and means for storing microaddress into said implicit register directly from a field contained in microinstructions accessed from said microstore.

Claim 42

The computer of claim 25 wherein said microaddress generation means includes a top-of-stack register and includes stack multiplexer control means for selecting microaddresses from said stack memory and said link memory for loading said top of stack register.

Claim 43

The computer of claim 25 including timing means for controlling said microaddresses generation means to provide microaddresses periodically each period of a computer clock signal.

Claim 44

The computer of claim 40 wherein said timing means includes means for overlapping the accessing of microaddresses and the accessing of microinstructions whereby the selection of the microaddress for the next microinstruction is concurrent with the access of the current microinstruction.

Claim 45

In a digital computer having a microstore for storing subroutines of microinstructions where the microinstructions are accessable when addressed by microaddress, to control the digital computer, the steps comprising, generating microaddresses to address said microstore by addressing a link memory and a stack memory, said link memory having locations for storing predetermined microaddresses for linking subroutines of microinstructions and said stack memory having locations for storing microaddresses in connection with the execution of microinstructions, using a link pointer pointing to locations in said link memory, controlling the addressing of said stack memory and controlling the addressing of said link memory with said link pointer to sequentially provide microaddresses from said link memory or said stack memory, counting said link pointer each time a microaddress is accessed from said link memory, addressing said microstore with the microaddress selected from said stack memory or said link memory.

Claim 46

In a digital computer having a microstore for storing subroutines of microinstructions where the microinstructions are accessable when addressed by microaddress, to control the digital computer, the steps comprising, generating microaddresses to address said microstore by addressing a link memory and a stack memory, said link memory having locations for storing predetermined microaddresses for linking subroutines of microinstructions and said stack memory having locations for storing microaddresses in connection with the execution of microinstructions, using a link pointer pointing to locations in said link memory, controlling the addressing of said stack memory and controlling the addressing of said link memory with said link pointer to sequentially provide microaddresses from said link memory or said stack memory, counting said link pointer each time a microaddress is accessed from said link memory, addressing said microstore with the microaddress selected from said stack memory or said link memory.

Claim 47

In the method of claim 42, the steps of, using a stack pointer for pointing to locations in said stack memory and to an empty location, controlling said stack pointer to control the accessing of microaddresses from said stack memory, selecting microaddresses from locations pointed to by said link pointer only when said stack pointer points to said empty location.

Claim 48

The method of claim 43 including counting said stack pointer away from a number representing said empty location for each microaddress loaded into said stack memory and counting said stack pointer toward the number representing said empty location for each microaddress accessed from said stack memory.