Semiconductor integrated circuit core probing for failure analysis

Claim 2

A semiconductor integrated circuit die comprising: a core circuitry including a plurality of internal nodes; a plurality of bonding pads located along peripheral edges of the die outside the core circuitry and connected to selected ones of the internal nodes to provide for external electrical connection to the selected internal nodes after packaging of the die; at least one predetermined probe point within the core circuitry that is not connected to a bonding pad; and a probe pad located within the core circuitry and electrically connected to the probe point so as to provide for external electrical connection to the probe point by contacting the probe pad to conduct failure analysis of the die.

Claim 3

A semiconductor integrated circuit die according to claim 1 wherein the internal core circuitry includes an embedded RAM circuit and the probe pad is connected to the RAM circuit so as to support failure analysis of the RAM circuit.

Claim 4

A semiconductor integrated circuit die according to claim 2 wherein multiple probe pads are formed adjacent the RAM circuit, each probe pad being connected to a respective RAM address line for directly addressing the RAM circuit to support locating a failure in the RAM circuit.

Claim 5

A semiconductor integrated circuit die according to claim 2 wherein the internal probe pad has an area in a range of approximately 25 to 100 microns.

Claim 6

A semiconductor integrated circuit die according to claim 2 wherein multiple probe pads are formed adjacent the RAM circuit, each probe point pad being connected to a respective RAM data I/O line to support locating a failure in the RAM circuit.

Claim 7

A semiconductor integrated circuit die according to claim 2 wherein the probe pad is covered with an insulative passivation layer prior to packaging.

Claim 8

An application-specific integrated circuit (ASIC) having a plurality of functional circuit blocks formed on a common substrate, wherein one of the functional circuit blocks is an embedded RAM block, and further comprising: a plurality of internal nodes, each connected to one or more of the functional circuit blocks; a plurality of bonding pads, variously connected to selected ones of the internal nodes to provide for external electrical connection to the selected internal nodes after packaging of the ASIC; at least one predetermined probe point within the embedded RAM block that is not connected to a bonding pad; and a probe pad electrically connected to the probe point so as to provide for external electrical connection to the probe point in support of failure analysis of the RAM block.

Claim 9

An application-specific integrated circuit (ASIC) having a plurality of functional circuit blocks formed on a common substrate, wherein one of the functional circuit blocks is an embedded RAM block, and further comprising: a plurality of internal nodes, each connected to one or more of the functional circuit blocks; a plurality of bonding pads, variously connected to selected ones of the internal nodes to provide for external electrical connection to the selected internal nodes after packaging of the ASIC; at least one predetermined probe point within the embedded RAM block that is not connected to a bonding pad; and a probe pad electrically connected to the probe point so as to provide for external electrical connection to the probe point in support of failure analysis of the RAM block.

Claim 10

An ASIC according to claim 7 wherein the probe pad is sized to receive a wafer test probe.

Claim 11

An ASIC according to claim 7 wherein the probe pad has an area smaller than the bonding pads.

Claim 12

An ASIC according to claim 7 wherein multiple probe points are selected and corresponding probe pads are formed about the embedded RAM block so as to enable bit mapping of the RAM block by connecting a programmed tester to the probe pads.

Claim 15

A method according to claim 11 wherein the internal probe pad is connected to a RAM circuit for accessing the RAM circuit without having to use surrounding logic circuits in the ASIC.

Claim 16

A method according to claim 11 wherein the removing step comprises selectively opening the passivation layer with a focused ion beam (FIB).

Claim 17

A method according to claim 11 wherein: said providing a test probe includes providing a probe card having a plurality of test probes arranged thereon in a predetermined pattern, the test probe pattern including at least one test probe positioned for contacting the exposed probe pad when the probe card is operatively positioned in contact with the ASIC; and wherein said applying the test probe comprises moving the probe card into a predetermined position in contacting alignment with the ASIC.

Claim 18

An improved integrated circuit probe card for failure analysis comprising: a rigid substrate having a central aperture sized for receiving an integrated circuit die when the die is mounted in operative relation to the probe card; a plurality of connectors formed in an outer portion of the substrate for electrical connection to a tester apparatus; a plurality of individual wire probes fixed to the substrate and extending generally from a region of the substrate adjacent the central aperture in a direction of and overhanging the central aperture for contacting corresponding pads on the integrated circuit die when the die is mounted in operative relation to the probe card; electrical conductors formed in the substrate for interconnecting each of the wire probes to a corresponding one of the connectors; and wherein at least one of the wire probes is sized and formed so as to extend into a core area of the integrated circuit die when the die is mounted in said operative relation to the probe card for contacting a probe pad formed within said core area of the die.

Claim 19

An improved integrated circuit probe card for failure analysis comprising: a rigid substrate having a central aperture sized for receiving an integrated circuit die when the die is mounted in operative relation to the probe card; a plurality of connectors formed in an outer portion of the substrate for electrical connection to a tester apparatus; a plurality of individual wire probes fixed to the substrate and extending generally from a region of the substrate adjacent the central aperture in a direction of and overhanging the central aperture for contacting corresponding pads on the integrated circuit die when the die is mounted in operative relation to the probe card; electrical conductors formed in the substrate for interconnecting each of the wire probes to a corresponding one of the connectors; and wherein at least one of the wire probes is sized and formed so as to extend into a core area of the integrated circuit die when the die is mounted in said operative relation to the probe card for contacting a probe pad formed within said core area of the die.

Claim 20

A probe card according to claim 15 wherein the wire probes include a first set of probes arranged for contacting corresponding bonding pads on the die, and a second set of probes for contacting internal probe pads located within the core circuitry on the die.

Claim 21

A probe card according to claim 15 wherein all of the wire probes are sized and formed so as to extend into a core area of the integrated circuit die when the die is mounted in said operative relation to the probe card for contacting corresponding probe pads formed within said core area of the die for conducting failure analysis.